Lateral DMOS Device With N-Type Adjusting Layer
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Solution Overview
Problem
High side LDMOS devices in BCD processes face limitations in operating voltage due to breakdown voltage constraints, which are difficult to increase without increasing on-resistance, making it challenging to implement higher voltage operations.
Innovation Solution
The introduction of an N-type adjusting layer, combined with a thicker P-type epitaxial layer and wider deep well cutout area, allows for increased breakdown voltage without elevating on-resistance, enabling higher operation voltages while maintaining device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of the P-type epitaxial layer is increased and the width of deep well cutout area is widened to raise breakdown voltage, then the breakdown voltage is improved, but the on-resistance increases
Solution Approach 1:
The invention divides the deep well structure into two functional zones: a first deep well region with wider width for voltage breakdown control, and a second deep well region with narrower width for resistance optimization. This segmentation allows independent optimization of each region's dimensions to simultaneously achieve high breakdown voltage and low on-resistance
Solution Approach 2:
Different regions of the deep well are assigned different width characteristics: the first deep well region has a wider width to enhance voltage breakdown performance, while the second deep well region has a narrower width to reduce on-resistance. This local differentiation of structural quality resolves the contradiction between the two opposing requirements
Data Source
AI summary
An LDMOS device and a method for fabricating the same that may include a first conductivity-type semiconductor substrate having an active area and a field area; a second conductivity-type deep well formed on the first conductivity-type semiconductor substrate; a second conductivity-type adjusting layer located in the second conductivity-type deep well; a first conductivity-type body formed in the second conductivity-type deep well; an insulating layer formed on the first conductivity-type semiconductor substrate in the active area and the field area; a gate area formed on the first conductivity-type semiconductor substrate in the active area; a second conductivity-type source area formed in the first conductivity-type body; a second conductivity-type drain area formed in the second conductivity-type deep well. Accordingly, such an LDMOS device has a high breakdown voltage without an increase in on-resistance.