LDMOS Breakdown Voltage via N-Well Field Buffering
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Solution Overview
Problem
Conventional LDMOS transistors face reduced breakdown voltage due to high surface electric fields, which is exacerbated by device scaling, and widening the source finger to increase breakdown voltage compromises layout flexibility and further scaling.
Innovation Solution
A semiconductor structure with a diode structure at the finger end and a RESURF transistor configuration, where the N-type well region has varying impurity concentrations to reduce surface electric fields and enhance field buffering, allowing for improved breakdown voltage without sacrificing layout flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the width of the finger shaped source is widened to enlarge the curvature radius of the finger end, then breakdown voltage increases, but layout flexibility is sacrificed
Solution Approach 1:
The patent applies local quality by creating a specialized field buffer region with distinct doping characteristics (different impurity concentration and depth) at the finger end area where high electric field occurs. This localized structural modification addresses the high field problem specifically at the critical location without requiring changes to the overall source finger dimensions, thereby maintaining layout flexibility while improving breakdown voltage.
2Productivity
If device size and width of source are decreased to enable scaling-down, then integration density increases, but breakdown voltage decreases due to increased electric field
Solution Approach 1:
The patent employs parameter changes by modifying the doping parameters (impurity concentration and junction depth) to create a field buffer region with optimized electrical characteristics. By adjusting these parameters, the invention achieves enhanced field buffering capability that compensates for the increased electric field effects caused by device scaling, allowing continued scaling while maintaining breakdown voltage.
3Device complexity
If conventional LDMOS structure is used, then device simplicity is maintained, but surface electric field causes reduced breakdown voltage
Solution Approach 1:
The patent applies segmentation by dividing the doped body region into functionally distinct zones: a standard source region and a specialized field buffer region at the finger end. This segmentation allows the majority of the device to maintain the simple conventional LDMOS structure while isolating the field buffering function to a specific segment, thus minimizing the increase in overall device complexity while effectively addressing the breakdown voltage issue.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The semiconductor structure effectively reduces surface electric field density and increases breakdown voltage, improving device performance and enabling further scaling while maintaining layout flexibility.
Implementation Method 1
The second type bar regions are inter-diffused to form a second type continuous region adjoining the second type well region
Data Source
AI summary
A method for fabrication of a semiconductor device is provided. A first type doped body region is formed in a first type substrate. A first type heavily-doped region is formed in the first type doped body region. A second type well region and second type bar regions are formed in the first type substrate with the second type bar regions between the second type well region and the first type doped body region. The first type doped body region, the second type well region, and each of the second type bar regions are separated from each other by the first type substrate. The second type bar regions are inter-diffused to form a second type continuous region adjoining the second type well region. A second type heavily-doped region is formed in the second type well region.