LDMOS and Poly Resistor Integration via Single Mask
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Solution Overview
Problem
The integration of low on-state resistance (Rdson) laterally diffused metal oxide semiconductor (LDMOS) devices with high sheet resistance polysilicon resistors requires additional masks, leading to increased costs and suboptimal doping profiles, which are not cost-effective and do not fully optimize LDNMOS performance.
Innovation Solution
A method is developed to form both low Rdson LDNMOS and high sheet resistance poly resistors using the same mask, involving the creation of shallow trench isolation regions, P-wells, N-drift regions, and resistance adjustment implants within the polysilicon layer without passing through it, allowing for the formation of a gate stack and poly resistor with a single mask set.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If additional masks are used for poly resistor formation and LDMOS drain implant, then device performance can be optimized, but manufacturing cost increases
Solution Approach 1:
The patent combines the poly resistor formation and LDMOS drain implant into a single mask step. The same mask that defines the poly resistor regions is used to define the drain implant regions, eliminating the need for separate masking steps and reducing manufacturing complexity while maintaining device performance
Solution Approach 2:
The patent makes the poly mask serve multiple functions: it defines both the high sheet resistance poly resistor regions and the LDMOS drain implant regions. This multi-functional use of a single mask reduces the total number of masking steps required in the fabrication process
2Ease of manufacture
If standard N-well is used for core device, then integration cost is reduced, but LDMOS drain resistance cannot be sufficiently reduced
Solution Approach 1:
The patent applies local quality by creating high-concentration N-type doping specifically in the LDMOS drain regions using the poly mask, while maintaining standard N-well characteristics in other areas. This localized high-concentration doping reduces LDMOS drain resistance without requiring a complete change to the standard N-well process
Solution Approach 2:
The patent changes the doping concentration parameter locally in the LDMOS drain regions by using additional N-type implants through the poly mask openings. This increases the dopant concentration in specific regions to reduce resistance while maintaining overall process compatibility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a 30% improvement in linear current and a 20% reduction in Rdson while maintaining breakdown voltage, achieving optimized performance without the need for additional masks, thus reducing integration costs and improving device efficiency.
Implementation Method 1
performing an N-drain implant between the second and third STI regions with a third mask; performing a resistance adjustment implant in, but not through, the poly-silicon layer with the third mask
Data Source
AI summary
A method for forming a low Rdson LDNMOS and a high sheet resistance poly resistor and the resulting device are provided. Embodiments include forming first, second, and third STI regions in a substrate; forming a P-well in the substrate around the first STI region with a first mask; forming an N-drift region in the substrate between the P-well and the third STI region with the first mask; forming a dielectric layer over the substrate; forming a poly-silicon layer over the dielectric layer; performing an N-drain implant between the second and third STI regions with a second mask; performing a resistance adjustment implant in, but not through, the poly-silicon layer with the second mask; and patterning the poly-silicon and dielectric layers subsequent to performing the resistance adjustment implant to form a gate stack and a poly resistor, the poly resistor being formed over the third STI region and laterally separated from the gate stack.