LDMOS P-TOP Region Grounding for Low On-Resistance
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Solution Overview
Problem
LDMOS devices face a challenge in maintaining high breakdown voltage while keeping on-resistance (Ron) low, as the floating P-TOP region accumulates charges, leading to decreased breakdown voltage and manufacturing instability.
Innovation Solution
The P-TOP region is grounded by forming a high concentration second conductive connection region on the surface of the first P-TOP region, connected to a ground line through a contact line, without increasing the pitch of the semiconductor device, allowing for stable manufacturing and reduced Ron.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the P-TOP region is made floating to reduce on-resistance, then Ron decreases, but breakdown voltage decreases due to charge accumulation
Solution Approach 1:
The P-TOP region is segmented into multiple regions with different doping concentrations (first P-TOP region with lower concentration and second P-TOP region with higher concentration), allowing each segment to serve different functions: the first region reduces on-resistance while the second region manages breakdown voltage by controlling charge accumulation
Solution Approach 2:
Different regions of the P-TOP structure are given different local properties through varying doping concentrations. The first P-TOP region has lower doping to minimize resistance, while the second P-TOP region has higher doping to control charge accumulation and maintain breakdown voltage, creating local quality variations that resolve the contradiction
2Reliability
If the P-TOP region is grounded to stabilize manufacturing, then manufacturing stability improves, but on-resistance increases due to increased pitch
Solution Approach 1:
Instead of grounding the entire P-TOP region (which would require increasing pitch in the planar dimension), the invention introduces a vertical dimension by creating multiple P-TOP regions at different depths with different doping concentrations. This allows grounding functionality to be achieved through vertical structuring rather than horizontal expansion, maintaining compact pitch while improving manufacturing stability
3Reliability
If the pitch of the P-TOP region is increased to form grounding structure, then manufacturing stability improves, but Ron increases due to larger device area
Solution Approach 1:
The invention transitions from a two-dimensional planar grounding approach (which increases pitch and device area) to a three-dimensional vertical approach. By forming P-TOP regions at different depths with different doping concentrations, the grounding function is achieved within the existing planar footprint, avoiding increases in both pitch and overall device area
Data Source
AI summary
A laterally-diffused metal oxide semiconductor (LDMOS) device and method of manufacturing the same are provided. The LDMOS device can include a drift region, a source region and a drain region spaced a predetermined interval apart from each other in the drift region, a field insulating layer formed in the drift region between the source region and the drain region, and a first P-TOP region formed under the field insulating layer. The LDMOS device can further include a gate polysilicon covering a portion of the field insulating layer, a gate electrode formed on the gate polysilicon, and a contact line penetrating the gate electrode, the gate polysilicon, and the field insulating layer.