LDMOS Recessed Channel Integration for Leakage and Breakdown Control
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Solution Overview
Problem
Integration of laterally-diffused metal-oxide semiconductor (LDMOS) devices with low voltage gate structures in advanced technology nodes leads to leakage issues and mismatch due to excessive divots in shallow trench isolation structures, causing junction leakage and poor oxide quality.
Innovation Solution
The integration scheme involves forming LDMOS devices with a recessed channel region and using thermally grown oxide (LOCOS) to reduce lateral space, improve breakdown voltage, and enhance oxide quality by forming shallow trench isolation structures with a planar surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If LDMOS devices are integrated with low voltage gate structures on a single chip, then device functionality and integration are improved, but leakage issues and junction leakage occur due to excessive divots in shallow trench isolation structures
Solution Approach 1:
The patent transitions from planar shallow trench isolation to a three-dimensional recessed channel structure. By recessing the channel region below the surface level and forming isolation structures that extend into the substrate, the design eliminates divot formation at the interface between LDMOS and low voltage devices, solving the leakage problem while maintaining integration.
Solution Approach 2:
The patent applies different isolation strategies to different regions: shallow trench isolation is used for low voltage devices while recessed channel structures with extended isolation are used for LDMOS devices. This localized approach allows each device type to have optimized isolation characteristics, preventing leakage at critical interfaces.
2Ease of manufacture
If conventional shallow trench isolation structures are used, then manufacturing simplicity is maintained, but interface traps and poor oxide quality result due to excessive divots
Solution Approach 1:
The patent moves from two-dimensional planar isolation to three-dimensional recessed structures. By etching the channel region below the surface and forming isolation that extends vertically into the substrate, the design eliminates the divot geometry that causes oxide quality issues while adding a controllable vertical dimension to the isolation structure.
3Area of stationary object
If lateral space is reduced for higher integration density, then chip area is minimized, but breakdown voltage performance deteriorates due to increased lateral electric field stress
Solution Approach 1:
The patent resolves the area-breakdown voltage tradeoff by transitioning to a vertical device architecture. By recessing the channel below the surface and forming vertical drift regions, the design achieves high breakdown voltage through vertical field control rather than lateral spacing, enabling high integration density without sacrificing voltage handling capability.
Solution Approach 2:
The patent employs composite doping profiles and material structures in the vertical drift region, combining different semiconductor materials and doping concentrations to optimize both the electric field distribution for high breakdown voltage and the vertical space utilization for compact integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces resistance (Rdson) and improves breakdown voltage performance by minimizing lateral space and interface traps, resulting in better reliability and reduced leakage.
Implementation Method 1
thermally grown oxide (LOCOS) to reduce lateral space, improve breakdown voltage, and enhance oxide quality
Data Source
AI summary
The present disclosure relates to semiconductor structures and, more particularly, to a transistor integration scheme and methods of manufacture. The structure includes: a first device on a semiconductor substrate; and a second device on the semiconductor substrate, the second device having a recessed channel region below a surface of the first device.