LDMOS Transistor RESURF Structure for Breakdown Voltage Trade-off
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Solution Overview
Problem
There is a need for solid-state circuits that can operate at higher frequencies, particularly in the microwave range, where LDMOS transistors with high breakdown voltage and low on-resistance are desirable for power amplifier circuits, but these parameters are inversely influenced by design changes.
Innovation Solution
A semiconductor device with a RESURF structure, including a doped buried layer spaced from the front and rear surfaces, coupled with the channel and body contact regions of an LDMOS transistor, and a field plate extending from the gate towards the drain region, which reduces the electric field and achieves a trade-off between high breakdown voltage and low on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the drift length is increased, then the breakdown voltage is improved, but the on-resistance is increased
Solution Approach 1:
The patent introduces a vertical buried layer structure at a third depth below the front surface, adding a vertical dimension to the traditional lateral drift region design. This buried layer creates an extended depletion region that increases breakdown voltage without requiring an increase in lateral drift length, thereby avoiding the penalty of increased on-resistance. The vertical extension of the depletion region through the buried layer allows independent optimization of breakdown voltage and on-resistance parameters.
Solution Approach 2:
The patent changes the doping parameters by introducing a buried layer with a second conductivity type at a specific depth (third depth) below the front surface. By controlling the doping concentration, depth, and lateral extent of this buried layer, the electric field distribution is modified to achieve higher breakdown voltage while maintaining low on-resistance. The parameter changes in the doping profile enable simultaneous optimization of both contradictory parameters.
2Strength
If the drift length is increased, then the breakdown voltage is improved, but the device complexity is increased
Solution Approach 1:
The patent segments the depletion region into multiple zones: the lateral drift region and the vertical depletion region extending from the buried layer. This segmentation allows the breakdown voltage enhancement to be achieved through the vertical buried layer structure rather than extending the lateral drift length, thereby reducing device complexity while maintaining improved breakdown performance.
Solution Approach 2:
By transitioning from a purely lateral drift region design to a structure incorporating a vertical buried layer at a third depth, the patent achieves breakdown voltage enhancement in the vertical dimension. This dimensional change avoids the need for increased lateral drift length and reduces overall device complexity while achieving the desired electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The RESURF structure enhances the breakdown voltage while maintaining low on-resistance, improving the performance of LDMOS transistors for higher frequency operations.
Implementation Method 1
A LDMOS transistor with a RESURF structure includes a doped buried layer arranged in a semiconductor substrate, spaced at a distance from a front surface and a rear surface of the substrate and coupled with a channel region and a body contact region of the LDMOS transistor
Implementation Method 2
implanting a self-depleting layer with a dopant concentration of a first conductivity type within a semiconductor substrate
Data Source
AI summary
In an embodiment, a semiconductor device includes a semiconductor substrate having a bulk resistivity ρ≥100 Ohm.cm, a front surface and a rear surface. An LDMOS transistor is arranged in the semiconductor substrate. A RESURF structure including a doped buried layer is arranged in the semiconductor substrate. The LDMOS transistor includes a body contact region doped with a first conductivity type, and a source region disposed in the body contact region and doped with a second conductivity type opposite the first conductivity type. The source region includes a first well and a second well of the same second conductivity type. The first well is more highly doped than the second well. The first well extends from inside the body contact region to outside of a lateral extent of the body contact region in a direction towards a source side of a gate of the LDMOS transistor.