LDMOS Source-End Doping Layout for Reverse-Bias Self-Protection
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Solution Overview
Problem
N-type LDMOS devices face functional failures due to parasitic NPN structures being mistakenly turned on during reverse voltage-withstanding states, caused by hole current flow and voltage drops in the P-type well region, which reduces the self-protection capability of the device.
Innovation Solution
A semiconductor device design featuring a substrate with a drift region, a well region, and doped regions of opposite types, where the source-end doped region includes at least one first and one second doped region, linearly distributed and alternately connected, with a gate structure forming a channel region between them, reducing the voltage drop and preventing parasitic NPN structure activation. The manufacturing method involves forming a well region by etching and epitaxy, optimizing doping concentration and interface states for improved electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional N-type LDMOS device structure is used, then the device can operate in high current and high voltage modes, but the parasitic NPN structure is easily mistakenly turned on due to hole current flow and voltage drops in the P-type well region, reducing self-protection capability
Solution Approach 1:
The source-end doped region is segmented into multiple first doped regions and second doped regions of opposite doping types that are linearly distributed and alternately connected. This segmentation shortens the hole current flow path within the well region, reducing voltage drops and preventing parasitic NPN structure activation, thereby improving self-protection capability
Solution Approach 2:
The patent introduces doped regions with opposite doping types at the source-end with different local properties (alternating N-type and P-type regions). These locally differentiated doped regions create multiple short holes current paths, reducing the voltage drop across the well region and preventing parasitic NPN turn-on, thus enhancing reliability
2Reliability
If the hole current flow path in the well region is long, then the device structure is simpler, but the voltage drop increases causing parasitic NPN structure to be mistakenly turned on
Solution Approach 1:
By segmenting the source-end doped region into alternating first and second doped regions, the patent creates multiple short holes current paths. This segmentation effectively reduces the hole current flow path length within the well region, minimizing voltage drops and preventing parasitic NPN activation while maintaining structural simplicity
3Reliability
If the source-end doped region uses single doping type, then the manufacturing process is simpler, but the voltage drop cannot be effectively reduced to prevent parasitic NPN turn-on
Solution Approach 1:
The patent applies local quality by introducing doped regions with opposite doping types at specific locations (source-end) while keeping other regions conventional. This localized modification creates multiple short holes current paths to reduce voltage drop and prevent parasitic NPN activation, improving self-protection capability with minimal increase in device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively shortens the hole current flow path, reduces voltage drops, and enhances the self-protection capability of the semiconductor device by preventing parasitic NPN structure activation, while improving current uniformity and reducing resistance.
Implementation Method 1
forming a well region by etching and epitaxy
Data Source
AI summary
Disclosed is a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a drift region on a substrate, a well region on the drift region, a source-end doped region in the well region, a drain-end doped region on the drift region, and a gate structure which is located between a source end and a drain end, located at a position of the well region, and forms a channel region in the well region. The source-end doped region comprises a first doped region and a second doped region with opposite doping types, the channel region connects the first doped region and the drift region. The first doped region and the second doped region of the source end are equivalently close to the gate structure, a distance between the second doped region and a PN junction surface formed by the drift region and the well region is reduced.