LDMOS Ring Gate Structure for Low On-Resistance

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Solution Overview

Problem

Current high-voltage LDMOS devices have a T-shape or H-shape gate structure that results in higher resistance, limiting their performance and efficiency in power switching applications.

Innovation Solution

A lateral-diffusion metal-oxide semiconductor (LDMOS) device with a ring-shaped gate structure and specific conductive type regions, including body implant regions and source/drain regions, is designed to reduce on-resistance and improve performance by optimizing the gate-to-body capacitance and finger widths.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a T-shape or H-shape gate structure is used in high-voltage LDMOS devices, then the device can achieve high breakdown voltage capability, but the on-resistance increases and performance deteriorates

Engineering Contradiction:
Improvebreakdown voltage capabilityVSAvoidon-resistance
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The gate structure is divided into multiple fingers arranged in a ring shape, with each finger contributing to the overall breakdown voltage capability while the distributed configuration reduces the on-resistance by providing multiple parallel conduction paths. The ring shape further segments the current flow path to optimize both high-voltage withstand and low-resistance characteristics.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The gate structure transitions from a planar T-shape or H-shape configuration to a three-dimensional ring shape with vertical components. This dimensional change allows the gate to simultaneously achieve high breakdown voltage through vertical field control and low on-resistance through horizontal current distribution, resolving the contradiction between these two opposing requirements.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Loss of energy

If the gate structure is optimized to reduce on-resistance, then power switching efficiency improves, but the breakdown voltage capability may be compromised

Engineering Contradiction:
Improvepower switching efficiencyVSAvoidbreakdown voltage capability
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

Different regions of the ring-shaped gate structure have optimized local properties: the vertical portions provide high electric field control for breakdown voltage capability, while the horizontal connecting portions provide low-resistance current paths. This local optimization allows simultaneous achievement of high reliability and low energy loss.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The ring-shaped gate structure functions as a composite configuration combining vertical and horizontal elements, each optimized for different functions. The vertical segments contribute to voltage blocking capability while the horizontal segments contribute to current conduction, creating a composite structure that achieves both high breakdown voltage and low on-resistance.

Inventive Principle:
Principle #40Composite materials

Data Source

PatentUS11721757B2Semiconductor device
Publication Date: 2023.08.08 UNITED MICROELECTRONICS CORP
  • US11721757B2 patent drawing
  • US11721757B2 patent drawing
  • US11721757B2 patent drawing

AI summary

A LDMOS device includes a semiconductor layer on an insulation layer and a ring shape gate on the semiconductor layer. The ring shape gate includes a first gate portion, a second gate portion, and two third gate portions connecting the first gate portion and the second gate portion. The semiconductor device further includes a first drain region and a second drain region formed in the semiconductor layer at two sides of the ring shape gate, a plurality of source regions formed in the semiconductor layer surrounded by the ring shape gate, a plurality of body contact regions formed in the semiconductor layer and arranged between the source regions, and a first body implant region and a second body implant region formed in the semiconductor layer, respectively underlying part of the first gate portion and part of the second gate portion, and being connected by the body contact regions.