LDMOS-SCR ESD Protection with Reference Gate Control
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Solution Overview
Problem
High voltage and high speed ESD protection devices face challenges with large parasitic capacitance due to multiple fingers, which is incompatible with fast rise time requirements, and LDMOS-SCR devices struggle with reliable turn-on via drain-source avalanche breakdown.
Innovation Solution
An LDMOS-SCR ESD protection structure using a reference LDSCR device to control the gate voltage of a major LDSCR device, with adjustable RESURF layers to manage triggering voltage and snapback, allowing for controlled turn-on and reduced parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple fingers are used to handle high currents, then high voltage capability is improved, but parasitic capacitance increases which degrades fast rise time performance
Solution Approach 1:
The invention divides the LDMOS-SCR device into multiple discrete fingers (first finger, second finger, third finger, fourth finger) that are electrically connected in parallel. This segmentation allows the device to handle high currents and voltages distributed across multiple fingers while reducing the parasitic capacitance compared to a single large device, thereby maintaining fast rise time performance.
2Reliability
If drain-source avalanche breakdown is used to turn on LDMOS-SCR, then device activation is achieved, but reliable turn-on cannot be achieved due to voltage dispersion in the extended drain
Solution Approach 1:
The invention introduces a gate electrode as an intermediary control element that receives a control signal to activate the LDMOS-SCR device. This gate control mechanism provides precise and reliable turn-on by directly controlling the device activation, eliminating the voltage dispersion problems associated with relying solely on drain-source avalanche breakdown through the extended drain region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables reliable ESD protection for high frequency and high voltage applications by controlling the gate voltage of the LDSCR device, achieving earlier triggering and reducing parasitic capacitance, thus addressing the limitations of existing solutions.
Implementation Method 1
current from the reference LDSCR device is used to control the voltage on the gate of the major LDSCR device
Implementation Method 2
The reference LDSCR device may include a reduced surface field layer (RESURF layer), which may be defined by the p-well of the reference LDSCR device or by another RESURF layer and which defines a p-well-composite overlap in the reference LDSCR device
Data Source
AI summary
In an LDMOS-SCR ESD protection structure gate voltage of an ESD protection LDSCR is defined by connecting the gate to the source of a reference LDSCR. The reference LDSCR is implemented as a self-triggering device in which the snapback drain-source voltage (avalanche breakdown voltage) is controlled to be lower than that for the major LDSCR by adjusting the RESURF layer-composite overlap for the reference LDSCR to be different to that of the major LDSCR.