LDMOS Device With Segmented Isolation Projections

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Solution Overview

Problem

High on-state resistance in laterally diffused metal oxide semiconductor (LDMOS) devices degrades their performance when high voltage is applied, as the electrical channel under the gate structure experiences increased resistance and low saturation current, which is not adequately addressed by existing junction isolation technologies.

Innovation Solution

The implementation of a partially slotted shallow trench isolation (STI) structure near the drain side, with specific dimensions and configurations that reduce on-state resistance while maintaining breakdown voltage, by creating a shorter current conduction path and a 3-dimensional electric field that supports full depletion of the drift region.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If a high voltage is applied to the gate of an LDMOS device, then the device can operate in high voltage applications, but the electrical channel under the gate structure experiences higher on-state resistance and low saturation current

Engineering Contradiction:
Improvehigh voltage operation capabilityVSAvoidon-state resistance
Core Design Contradiction:
TemperatureVSReliability

Solution Approach 1:

The isolation structure is segmented into multiple projections instead of a continuous structure. These discrete projections are spaced apart to create slots that allow electric field penetration, reducing the on-state resistance by approximately 20% while maintaining the necessary isolation functionality and breakdown voltage characteristics

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The isolation structure transitions from a uniform continuous structure to a non-uniform segmented structure with varying projection dimensions and spacing. This local modification creates regions with different electric field distributions, allowing the structure to simultaneously provide isolation and reduce on-state resistance in specific areas

Inventive Principle:
Principle #3Local quality

2Ease of manufacture

If conventional junction isolation technology is used, then the device structure is simple to manufacture, but it does not adequately reduce on-state resistance

Engineering Contradiction:
Improveisolation structure fabricationVSAvoidon-state resistance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The isolation structure is divided into multiple discrete projections formed through a modified shallow trench isolation process. This segmentation is achieved by patterning the isolation dielectric layer to create spaced projections rather than a continuous barrier, enabling reduced on-state resistance while maintaining compatibility with standard semiconductor fabrication processes

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The isolation structure transitions from a two-dimensional planar configuration to a three-dimensional segmented structure with vertical projections. This dimensional change creates slots between projections that allow electric field penetration and reduce on-state resistance while maintaining the isolation function

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces on-state resistance by approximately 20% without significantly compromising breakdown voltage, enhancing the performance of LDMOS devices in high voltage applications.

Implementation Method 1

by creating a shorter current conduction path and a 3-dimensional electric field that supports full depletion of the drift region

Methodology Applied
Scientific EffectElectric Field: Electric Field

Implementation Method 2

reduces on-state resistance by approximately 20% without significantly compromising breakdown voltage

Methodology Applied
Scientific EffectElectrical Resistance: Electrical Resistance

Data Source

PatentUS8159029B2High voltage device having reduced on-state resistance
Publication Date: 2012.04.17 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US8159029B2 patent drawing
  • US8159029B2 patent drawing
  • US8159029B2 patent drawing

AI summary

A semiconductor device includes a semiconductor substrate, a source region and a drain region formed in the substrate, a gate structure formed on the substrate disposed between the source and drain regions, and a first isolation structure formed in the substrate between the gate structure and the drain region, the first isolation structure including projections that are located proximate to an edge of the drain region. Each projection includes a width measured in a first direction along the edge of the drain region and a length measured in a second direction perpendicular to the first direction, and adjacent projections are spaced a distance from each other.