LDMOS Breakdown Voltage via Segmented Spacer Recess

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Solution Overview

Problem

The breakdown voltage of self-aligned laterally-diffused metal-oxide semiconductor (LDMOS) devices is limited by the gate oxide thickness, which restricts their performance in low voltage range applications such as consumer electronics.

Innovation Solution

The method involves forming a semiconductor device with a gate and spacers, where a second spacer with a proximal and distal spacer portion defines a recess, allowing for increased spacing between the gate and the drain drift region, thereby enhancing breakdown voltage without tapering, and using a sacrificial gate portion that is laterally separated from the main gate to create a non-tapering second spacer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the gate oxide thickness is reduced to achieve lower operating voltage, then the device can operate in low voltage range (5-10V), but the breakdown voltage is limited and cannot be increased

Engineering Contradiction:
Improveoperating voltageVSAvoidbreakdown voltage
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The second spacer is divided into two separate spacer portions (first spacer portion and second spacer portion) that are laterally separated from each other. This segmentation allows the spacer to provide greater lateral spacing between the gate and drain drift region while maintaining structural integrity, thereby increasing breakdown voltage without requiring thicker gate oxide

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention transitions from vertical spacer configuration to lateral spacer configuration by placing the second spacer portions horizontally between the gate and drain drift region. This dimensional change enables increased lateral spacing that directly enhances breakdown voltage while keeping the gate oxide thickness thin for low voltage operation

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If the lateral width of the second spacer is increased to enhance breakdown voltage, then higher voltage handling capability is achieved, but the spacer may require tapering which complicates the structure

Engineering Contradiction:
Improvebreakdown voltageVSAvoidspacer structure
Core Design Contradiction:
ReliabilityVSShape

Solution Approach 1:

By segmenting the second spacer into two laterally separated portions, the invention achieves increased lateral width without requiring tapering of a single continuous spacer. Each spacer portion can maintain a simple rectangular cross-section, avoiding structural complexity while providing the necessary spacing for high breakdown voltage

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Instead of increasing the vertical height or using a tapered single spacer, the invention inverts the approach by using two separate spacer portions placed laterally. This inverted configuration achieves the same spacing function with simpler, non-tapering geometry

Inventive Principle:
Principle #13The other way round (Inversion)

3Ease of manufacture

If a self-aligned structure is maintained to simplify manufacturing, then fabrication complexity is reduced, but the breakdown voltage enhancement is limited

Engineering Contradiction:
Improvefabrication complexityVSAvoidbreakdown voltage
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The sacrificial gate portion is formed preliminarily during gate fabrication, and the second spacer portions are formed using this sacrificial structure as a reference. This preliminary action enables self-aligned formation of the complex dual-spacer configuration without requiring additional alignment steps, maintaining manufacturing simplicity while achieving enhanced breakdown voltage

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP4080583A1Semiconductor device and method of making a semiconductor device
Publication Date: 2022.10.26 NXP USA INC
  • EP4080583A1 patent drawingFigure 1~3
  • EP4080583A1 patent drawingFigure 4A~4C
  • EP4080583A1 patent drawingFigure 4D~4F

AI summary

A laterally-diffused metal-oxide semiconductor, "LDMOS", device and a method of making the same. The device includes a gate located on a major surface of a semiconductor die, a source region located in the die on a first side of the gate, a drain drift region located in the die on a second side of the gate opposite the first side, a first spacer located adjacent to a first sidewall of the gate on the first side of the gate, and a second spacer located adjacent to a second sidewall of the gate on the second side of the gate. The second spacer is located between the gate and the drain drift region. The second spacer comprises a proximal spacer portion and a distal spacer portion. The proximal spacer portion is located between the gate and the distal spacer portion. The proximal spacer portion and the distal spacer portion define a recess.