LDMOS Transistor Segmented Sub-Source Layout for Breakdown Voltage
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Solution Overview
Problem
Conventional laterally diffused metal oxide semiconductor (LDMOS) transistors face issues with excessive current concentration and heat dissipation due to layout design, leading to reduced breakdown voltage and increased resistance, particularly in high-voltage applications.
Innovation Solution
The design incorporates a substrate with a drain and source formed as multiple sub-sources and sub-drains, along with a gate and a drift layer, where the channels are strategically removed at corners to reduce current density and a chamfered gate acts as a field plate, and the drift layer surrounds the drain to enhance breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the drain and source are formed as a single closed structure surrounding the center, then the layout is simple and manufacturing is easier, but excessive current concentration occurs at corners leading to reduced breakdown voltage
Solution Approach 1:
The patent segments the drain and source regions into multiple sub-drains and sub-sources arranged in parallel, replacing the single closed-loop structure. This segmentation distributes the current flow across multiple paths, eliminating corner current concentration while maintaining manufacturing feasibility through standardized repetitive patterns.
Solution Approach 2:
The patent introduces asymmetry by removing channels at corner positions and implementing chamfered gate structures, breaking the symmetric current distribution pattern that causes corner concentration. This asymmetric modification redirects current flow to more uniform distribution across the device area.
2Temperature
If parallel numbers and length of transistors are increased to reduce current density, then heat dissipation improves, but breakdown voltage decreases
Solution Approach 1:
The patent segments the transistor structure into multiple parallel sub-units with controlled spacing, achieving current density reduction through spatial distribution rather than simply increasing total transistor count. The segmented layout with optimized pitch maintains breakdown voltage by preventing excessive lateral diffusion while improving heat dissipation through distributed current paths.
Solution Approach 2:
The patent transitions from increasing current capacity in the planar dimension (more parallel transistors) to optimizing the vertical dimension (drift layer thickness and doping concentration), thereby improving heat dissipation without compromising breakdown voltage through vertical field control.
3Reliability
If the N-drift region concentration is decreased and length is increased to increase breakdown voltage, then resistance increases
Solution Approach 1:
The patent applies local quality by implementing non-uniform doping concentration profiles in the drift region, with higher concentration near the surface to reduce resistance and lower concentration deeper in the bulk to maintain breakdown voltage. This spatially varying doping optimization simultaneously addresses both resistance and breakdown voltage requirements.
Solution Approach 2:
The patent optimizes multiple parameters including drift layer thickness, doping concentration, and junction depth to achieve the desired balance between breakdown voltage and resistance. By carefully controlling these parameters within specific ranges, the patent achieves low resistance while maintaining high breakdown voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases the breakdown voltage and improves heat dissipation by reducing current density and parasitic capacitance, effectively addressing the limitations of conventional LDMOS transistor layouts.
Implementation Method 1
a chamfered gate acts as a field plate
Implementation Method 2
replaces the heavy-doped region with a lightly doped N-drift region to buffer the most voltage drops applied from the drain to obtain the high breakdown voltage
Implementation Method 3
A P-sink 6, a P-type heavy-doped region, is connected with the source 1 and a substrate 7 to reduce the parasitic capacitance therebetween, improving heat dissipation
Data Source
AI summary
A laterally diffused metal oxide semiconductor transistor. The laterally diffused metal oxide semiconductor transistor includes a substrate, a drain formed thereon, a source formed on the substrate, comprising a plurality of individual sub-sources respectively corresponding to various sides of the drain, a plurality of channels formed in the substrate between the sub-sources and the drain, a gate overlying a portion of the sub-sources and the channels, and a drift layer formed in the substrate underneath the drain.