LDMOS Transistors with Segmented Vertical Gate Dielectrics
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Solution Overview
Problem
Conventional LDMOS transistors with a single dielectric layer face challenges in achieving both high breakdown voltage and low on-resistance due to the need for a uniform dielectric thickness, which can lead to suboptimal performance and manufacturing difficulties, especially in forming trench structures with varying dielectric thickness.
Innovation Solution
The development of LDMOS transistors with a vertical gate structure featuring multiple dielectric sections, allowing for independent selection of separation distances between the gate conductor and the semiconductor structure, which enables high breakdown voltage and low on-resistance by optimizing gate-to-drain and gate-to-source characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single uniform dielectric layer is used in conventional LDMOS transistors, then manufacturing is simplified, but both high breakdown voltage and low on-resistance cannot be achieved simultaneously
Solution Approach 1:
The gate dielectric layer is divided into multiple distinct dielectric sections (first gate dielectric layer, second gate dielectric layer, third gate dielectric layer) with different thicknesses positioned at different locations. This segmentation allows each section to be optimized independently for its specific function: thicker sections for breakdown voltage and thinner sections for low on-resistance, resolving the contradiction between reliability and device complexity.
Solution Approach 2:
Different dielectric thicknesses are applied at different locations within the gate structure. The first gate dielectric layer has a greater thickness than the second gate dielectric layer, creating local variations in dielectric properties. This local quality approach enables optimal electrical characteristics at each location, achieving both high breakdown voltage and low on-resistance simultaneously.
2Manufacturing precision
If a uniform dielectric thickness is used, then manufacturing precision is easier to maintain, but optimal transistor performance cannot be achieved
Solution Approach 1:
The manufacturing process is segmented into distinct steps for forming different dielectric layers with different thicknesses. Each dielectric layer can be deposited and controlled independently, allowing precise thickness control for each section while maintaining overall manufacturing feasibility through systematic process breakdown.
Solution Approach 2:
The gate dielectric structure is prepared in advance with specifically designed varying thicknesses before transistor operation. The first, second, and third gate dielectric layers are formed with predetermined thickness relationships during the fabrication process, enabling optimal performance to be built-in rather than adjusted later.
3Reliability
If varying dielectric thickness is implemented, then optimal electrical characteristics are achieved, but manufacturing complexity increases
Solution Approach 1:
The complex requirement for varying dielectric thickness is segmented into manageable discrete layers that can be formed using standard semiconductor fabrication techniques. Each gate dielectric layer serves a specific thickness function, making the overall complex structure achievable through systematic sequential processing rather than requiring complex single-step processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for flexible transistor configuration and manufacturing, promoting small transistor pitch and high performance by independently controlling separation distances to achieve desired electrical characteristics, while being compatible with CMOS processes and suitable for forming trench capacitors.
Implementation Method 1
A positive voltage VGS applied between gate electrode 116 and source electrode 104 creates negative charges in silicon semiconductor structure 102 under silicon dioxide layer 118, causing a minority-carrier channel to form in a region 136 of p-body 126
Implementation Method 2
This channel has excess electrons and will therefore conduct current. Consequentially, current will flow in the lateral 138 direction through silicon semiconductor structure 102 from drain n+ region 132 to source n+ region 130
Implementation Method 3
When positive voltage VDS is applied across drain electrode 108 and source electrode 104, a p-n junction at the interface of n-well 124 and p-body 126 is reversed biased. Consequentially, essentially no current flows from drain electrode 108 to source electrode 104 by default
Implementation Method 4
The relative dopant concentration of drain n+ region 132 and n-well 124 causes a portion of n-well 124 referred to as a drift region 134 to carry the majority of voltage VDS, thereby enabling LDMOS transistor 100 to support a relatively large value of VDS without breakdown
Data Source
AI summary
A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor includes a silicon semiconductor structure and a vertical gate. The vertical gate includes (a) a first gate conductor and a second gate conductor each extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure in a thickness direction, (b) a first separation dielectric layer separating the first gate conductor from the second gate conductor within the vertical gate, and (c) a gate dielectric layer separating each of the first gate conductor and the second gate conductor from the silicon semiconductor structure.