LDMOS Manufacture Method Using Self-Aligned Implantation
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Solution Overview
Problem
The existing manufacture methods for lateral double-diffused metal-oxide-semiconductor field effect transistors (LDMOS) face challenges in reducing source-drain on-state resistance while maintaining high breakdown voltage, due to limitations in photolithography capacity and complex process steps, leading to large device sizes and high resistance.
Innovation Solution
A modified manufacture method that includes forming a drift region and a gate structure on a substrate, with self-aligned implantation techniques to reduce the size of implantation regions and simplify the process, using barrier layers and isotropic/anisotropic etching to control the width of the implantation regions, and forming a dielectric layer and passivation layer to reduce the source-drain on-state resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If photolithography implantation is used to form implantation regions in the source region, then the manufacturing process is established, but the device size becomes large and source-drain on-state resistance becomes high due to photolithography capacity limitations
Solution Approach 1:
The patent uses self-aligned implantation where the gate structure and previously formed doped regions serve as alignment references for subsequent implantation steps. The implantation regions are formed by aligning with the gate structure rather than requiring separate photolithography patterning, allowing the process to be self-referencing and eliminating photolithography dimension limitations
Solution Approach 2:
The patent replaces photolithography-based patterning with direct self-aligned implantation techniques. Instead of using optical systems to define implantation region boundaries, the method uses physical alignment with the gate structure and ion implantation geometry to define regions, substituting optical mechanical systems with direct ion beam positioning
2Ease of manufacture
If photolithography implantation is used to form implantation regions in the source region, then the manufacturing process is established, but the source-drain on-state resistance becomes high
Solution Approach 1:
The self-aligned implantation process uses the gate structure and existing doped regions as alignment references, ensuring precise positioning of implantation regions. This precision enables optimal doping profiles that reduce source-drain resistance while maintaining manufacturing feasibility
Solution Approach 2:
The patent changes the approach from photolithography-defined dimensions to implantation geometry-defined dimensions. By controlling implantation angle, energy, and alignment with gate structure, the doping concentration and region boundaries are optimized to minimize source-drain resistance
3Ease of manufacture
If multiple photoresist layers are used to form implantation regions, then the manufacturing process can be completed, but the process complexity increases and operation becomes difficult
Solution Approach 1:
The gate structure and previously formed features serve as self-aligned masks and references for subsequent implantation steps. This eliminates the need for multiple photoresist deposition and patterning cycles, reducing process complexity while maintaining manufacturing capability
Solution Approach 2:
The patent combines multiple implantation steps into a self-aligned sequence where the gate structure serves multiple functions: as a mask, as an alignment reference, and as a defining feature for implantation regions. This merging of functions reduces the number of separate patterning operations required
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces the size of the device and the source-drain on-state resistance, simplifies the manufacturing process, and improves the performance of LDMOS by minimizing the space between gate conductor layers and optimizing implantation region sizes.
Implementation Method 1
implanting ions to form a first doped region
Implementation Method 2
forming an opening by etching
Data Source
AI summary
The present disclosure provides a manufacture method of an LDMOS. The manufacture method includes: forming a drift region in a substrate; forming a gate structure on the substrate, the gate structure defining a source region and a drain region which are separated from each other, and the gate structure including a gate oxide layer and a gate conductor layer which are successively stacked on the substrate; forming a first doped region in the source region, wherein the first doped region is surrounded by the drift region; forming a first barrier layer with a first opening on the source region and in connect with sidewall of the gate structure; forming a first implantation region in the source region through self-aligned implantation on the basis of the first opening of the first barrier layer; and forming a second implantation region and a third implantation region respectively.