Self-Biased Isolation in LDMOS Devices
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Solution Overview
Problem
LDMOS devices face breakdown issues due to high voltage stress between the body or drift region and the buried isolation layer, limiting breakdown voltage and degrading electrostatic discharge (ESD) and safe operating area (SOA) performance, with previous solutions introducing fabrication challenges or degrading performance.
Innovation Solution
Implementing a self-biased isolation structure where a depleted well region is used to partially lift the isolation potential, reducing voltage stress between isolation and drift regions, and forming an electrical link between the body and buried isolation layer without increasing device size or adding fabrication steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If biasing is applied to lift isolation potential, then breakdown voltage increases, but field stress between isolation layer and body/drift region increases causing breakdown
Solution Approach 1:
A depleted well region is introduced as an intermediary structure between the body/drift region and the buried isolation layer. This well region establishes an electrical link that partially lifts the isolation potential while distributing the voltage stress, preventing direct high-field stress between the isolation layer and body/drift region. The well region acts as a mediator that enables breakdown voltage enhancement without proportionally increasing field stress.
2Object-affected harmful factors
If isolation regions are biased at drain voltage to deplete regions, then electric field reduction is achieved, but field stress between isolation layer and body increases
Solution Approach 1:
The electrical link between the body/drift region and the buried isolation layer is segmented into multiple stages through the introduction of the depleted well region. Instead of a direct electrical connection that would create high field stress, the voltage transition is divided into two segments: one across the drift region and another across the well region. This segmentation allows the isolation potential to be partially lifted while distributing the electric field stress across multiple interfaces, thereby maintaining electric field control while enhancing breakdown voltage.
3Reliability
If previous efforts to address breakdown are implemented, then breakdown voltage is improved, but fabrication challenges or performance degradation occurs
Solution Approach 1:
The depleted well region serves multiple functions simultaneously: it establishes the electrical link for partial isolation potential lifting, acts as a depletion region to control electric field distribution, and provides a pathway for carrier transport. By combining these functions into a single structure formed through standard implantation and depletion processes, the solution avoids additional fabrication steps while achieving breakdown voltage enhancement without performance degradation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases breakdown voltage levels and improves the safe operating area of LDMOS devices while maintaining performance parameters and avoiding fabrication cost increases.
Implementation Method 1
a depletion region disposed in the semiconductor substrate and having a conductivity type in common with the buried doped isolation barrier and the body region, the depletion region reaching a depth in the semiconductor substrate to be in contact with the buried doped isolation layer. The depletion region establishes an electrical link between the buried doped isolation layer and the body region such that the buried doped isolation layer is biased at a voltage level lower than the voltage applied to the body region.
Data Source
AI summary
A device includes a semiconductor substrate, a buried doped isolation layer disposed in the semiconductor substrate to isolate the device, a body region disposed in the semiconductor substrate and to which a voltage is applied during operation and in which a channel is formed during operation, and a depletion region disposed in the semiconductor substrate and having a conductivity type in common with the buried doped isolation barrier and the body region. The depletion region reaches a depth in the semiconductor substrate to be in contact with the buried doped isolation layer. The depletion region establishes an electrical link between the buried doped isolation layer and the body region such that the buried doped isolation layer is biased at a voltage level lower than the voltage applied to the body region.