LDMOS Source Doping Layout to Suppress Parasitic NPN Turn-On
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Solution Overview
Problem
LDMOS transistors face challenges in maintaining both ruggedness and low specific on-resistance (Rsp) during transient events, particularly in high-side applications, where parasitic NPN bipolar junction transistors can be triggered, leading to device failure.
Innovation Solution
The implementation of a P-type diffused well surrounding an N-type well with integrated back-gate and staggered source contacts, combined with selective N-type and P-type doping, reduces the counter-doping of the P-type well, thereby minimizing the base resistance of the parasitic NPN bipolar junction transistor and enhancing avalanche current immunity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If uniformly high levels of doping are used throughout the source region to ensure desired conductivity, then source conductivity is improved, but base resistance of the parasitic NPN BJT increases and ruggedness deteriorates
Solution Approach 1:
The source region is divided into two distinct zones with different doping concentrations: a first source region with higher doping concentration to maintain conductivity, and a second source region with lower doping concentration to reduce base resistance of the parasitic NPN BJT. This local differentiation allows each zone to fulfill its specific function without compromising the other.
Solution Approach 2:
The source region is segmented into multiple sub-regions (first source region, second source region, third source region) with different doping characteristics. The first source region has higher doping for conductivity, while the second and third regions have lower doping to minimize base resistance, creating a segmented structure that balances conflicting requirements.
2Reliability
If N-type source/drain implant is applied to the source region, then source conductivity is improved, but counter-doping of the P-type well increases base resistance
Solution Approach 1:
The N-type source/drain implant is selectively applied only to specific portions of the source region (first source region) while deliberately excluding other portions (second and third source regions). This localized application ensures that conductivity enhancement occurs where needed without introducing counter-doping that would increase base resistance in critical areas.
Solution Approach 2:
The harmful effect of N-type implant counter-doping is extracted and isolated to specific regions by using selective masking techniques. The implant is taken out from the entire source region and applied only where conductivity is needed, preventing the spread of counter-doping to the P-type well in regions where it would harmfully increase base resistance.
3Ease of manufacture
If low specific on-resistance is maintained to minimize cost, then die size is reduced, but ruggedness during avalanche breakdown deteriorates
Solution Approach 1:
Different regions of the source are assigned different doping concentrations optimized for their specific functions: heavily doped regions for low resistance contacts, and lightly doped regions for maintaining low base resistance during avalanche events. This local optimization allows the device to achieve both low specific on-resistance for cost efficiency and high ruggedness for reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves the ruggedness of LDMOS transistors by preventing the parasitic NPN BJT from turning on, maintaining higher drain voltage at failure and increasing avalanche current immunity without significantly increasing source resistance.
Implementation Method 1
The DWELL-P forms the body and channel of the LDMOS transistor(s); an N-type source/drain (NSD) implant and a P-type source/drain (PSD) implant into the DWELL-N can form a source, source contacts, and integrated back-gate (IBG)
Implementation Method 2
Removing all or portions of the NSD implant reduces the counter-doping of the DWELL-P and allows a parasitic NPN bipolar junction transistor (BJT) that is inherent in the LDMOS transistor to maintain a lower base resistance
Implementation Method 3
connections between the body region and the source region to maintain similar voltages and prevent turn-on of the parasitic NPN BJT
Data Source
AI summary
An integrated circuit has a P-type substrate and an N-type LDMOS transistor. The LDMOS transistor includes a boron-doped diffused well (DWELL-B) and an arsenic-doped diffused well (DWELL-As) located within the DWELL-B. A first polysilicon gate having first sidewall spacers and a second polysilicon gate having second sidewall spacers are located over opposite edges of the DWELL-B. A source/IBG region includes a first source region adjacent the first polysilicon gate, a second source region adjacent the second polysilicon gate, and an integrated back-gate (IBG) region located between the first and second source regions. The first source region and the second source region each include a lighter-doped source sub-region, the IBG region including an IBG sub-region having P-type dopants, and the source/IBG region includes a heavier-doped source sub-region.