LDMOS Source Plug Segmentation for Parasitic Capacitance Reduction
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Solution Overview
Problem
The miniaturization of semiconductor devices using LDMOS leads to increased parasitic capacitance, which degrades the performance and power efficiency of high-frequency power amplifiers in mobile communication devices, necessitating a solution to reduce capacitance while maintaining or improving device characteristics.
Innovation Solution
The semiconductor device design incorporates a laterally diffused MISFET structure with optimized source and drain contact arrangements, including separated source and drain plugs and wirings, to minimize parasitic capacitance and enhance power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the semiconductor device is miniaturized, then the device size is reduced, but the parasitic capacitance increases which degrades performance and power efficiency
Solution Approach 1:
The source contact is divided into multiple separated source contacts arranged in the first direction, and the drain contact is divided into multiple separated drain contacts. This segmentation reduces the overlapping area between source and drain contacts, thereby reducing parasitic capacitance while maintaining compact device dimensions
Solution Approach 2:
The source and drain contacts are arranged in a staggered configuration where they are shifted relative to each other in the first direction. This dimensional arrangement minimizes the vertical projection overlap between source and drain contacts, effectively reducing parasitic capacitance without increasing the horizontal footprint of the device
2Reliability
If the number of wiring layers is increased to improve electrical coupling, then the electrical performance is improved, but the parasitic capacitance and device complexity increase
Solution Approach 1:
The source wiring and drain wiring are merged into a single wiring layer instead of using separate wiring layers for each. This merging approach maintains effective electrical coupling between the contacts while reducing the total number of wiring layers, thereby lowering device complexity and parasitic capacitance
Data Source
AI summary
A semiconductor device with improved characteristics is provided. The semiconductor device includes a LDMOS, a source plug electrically coupled to a source region of the LDMOS, a source wiring disposed over the source plug, a drain plug electrically coupled to a drain region of the LDMOS, and a drain wiring disposed over the drain plug. The structure of the source plug of the semiconductor device is devised. The semiconductor device is structured such that the drain plug is linearly disposed to extend in a direction Y, and the source plug includes a plurality of separated source plugs arranged at predetermined intervals in the direction Y. In this way, the separation of the source plug decreases an opposed area between the source plug and the drain plug, and can thus decrease the parasitic capacitance therebetween.