LDMOS Source Region Fabrication via Large-Angle Implant
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Solution Overview
Problem
The existing methods for forming source regions in LDMOS devices are limited by photo-masking equipment capabilities, leading to larger source regions and alignment errors, which hinder the miniaturization of these devices for smaller power applications.
Innovation Solution
The process employs large-angle tilt dopants implantation, where dopants are implanted at an angle relative to the vertical direction of the LDMOS poly gate, using the gate and masking layers as a block layer to form smaller source regions without the need for traditional photo-masking steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional photo-masking steps are used to form source regions, then the process is simple and equipment requirements are standard, but the source region size is limited by photo-masking equipment capability and alignment errors occur
Solution Approach 1:
The patent changes the implantation angle parameter from the conventional small angle (typically 7-15 degrees) to a large angle (45-60 degrees). This parameter change enables the dopant profile to be defined by the gate sidewall geometry rather than photo-masking dimensions, achieving source region widths below the photo-masking equipment capability limit while maintaining process control
Solution Approach 2:
The patent replaces the photo-masking mechanical system with a self-aligned implantation system. Instead of using photo-resist patterns and masking layers to define source regions, the method uses the gate structure itself as the alignment reference and the large-angle implantation geometry to define the source region boundaries, eliminating alignment errors associated with photo-masking
2Area of moving object
If the N+/P+/N+ region area is reduced to make smaller source regions, then device size is reduced, but the minimum area is limited by photo-masking equipment capability
Solution Approach 1:
The gate structure serves itself as the alignment reference for source region formation. The gate sidewalls automatically define the implantation boundaries through their geometric relationship with the large-angle dopant trajectory, eliminating the need for separate photo-masking steps and achieving sub-photo-masking-limited dimensions with high precision
Solution Approach 2:
The patent transitions from two-dimensional planar definition (photo-masking on horizontal plane) to three-dimensional geometric definition (large-angle implantation where the dopant trajectory intersects the gate sidewalls). This dimensional change enables precise control of source region width by adjusting the implantation angle and gate thickness rather than being constrained by photo-masking resolution
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for precisely controlled, narrower source regions with reduced alignment errors, enabling the formation of smaller source regions, which is essential for smaller power devices in modern applications.
Implementation Method 1
implanting dopants of a second doping type into the well region through the opening of the masking layer to form the body region; implanting dopants of the first doping type into the body region in a manner of large-angle-tilt dopants implantation to form source regions
Data Source
AI summary
A method for fabricating a semiconductor device including: forming a block layer above a well region of a first doping type in a semiconductor substrate, wherein the block layer has an opening for defining a first region in an upper part of the well region and has sidewalls at sides of the opening; implanting dopants of a second doping type into the well region through the opening of the block layer to form the first region; implanting dopants of the first doping type into the first region in the manner of large-angle-tilt dopants implantation to form a second region for a first transistor, and to form a third region for a second transistor; and forming, for both of the first transistor and the second transistor, a fourth region between the second region and the third region.