LDMOS Source Region Segmentation for Rdson Reduction
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Solution Overview
Problem
The existing LDMOS devices face challenges in reducing their layout length and drain-source on-state resistance (Rdson) value, which limits their integration level and performance in deep-submicron semiconductor processes, as their dimensions must remain above critical sizes to withstand high voltage.
Innovation Solution
The proposed solution involves altering the layout of the LDMOS device by rearranging the source contact regions and doped regions to be alternately arranged along the gate direction, allowing for a shorter layout length while maintaining performance, and using butting contact plugs to connect these regions, thereby reducing the overall device length and Rdson value.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the dimensions of LDMOS device regions are maintained above critical sizes to withstand high voltage, then the device reliability is improved, but the layout length increases and integration level deteriorates
Solution Approach 1:
The source region is segmented into multiple source contact regions and source doped regions that are alternately arranged. This segmentation allows the current to flow through multiple parallel paths, reducing the overall layout length while maintaining the high voltage withstanding capability through the distributed structure.
Solution Approach 2:
The patent transitions from a conventional linear arrangement of source regions to an alternating pattern along the gate direction. This dimensional reorganization allows current flow paths to be distributed along the gate length direction rather than requiring extended lateral spacing, thereby reducing layout length while preserving voltage blocking performance.
2Reliability
If the dimensions of LDMOS device regions are maintained above critical sizes to withstand high voltage, then the device reliability is improved, but the drain-source on-state resistance increases
Solution Approach 1:
The source region is divided into multiple source contact regions and source doped regions arranged alternately along the gate direction. This creates multiple parallel current flow paths that reduce the overall on-state resistance while maintaining adequate spacing and doping levels to ensure high voltage withstanding capability.
Solution Approach 2:
The alternating arrangement of source contact regions and source doped regions creates local variations in doping concentration and contact density. This local quality optimization allows current to flow through low-resistance paths where contact regions are present, while maintaining high voltage blocking capability in the doped regions, thereby reducing overall on-state resistance without compromising reliability.
Data Source
AI summary
A MOS device includes a semiconductor substrate having a first conductive type, a source region, a gate structure, and a drain region having a second conductive type. The gate structure is formed on the semiconductor substrate and substantially parallel to a first direction. The source region and the drain region are both disposed in the semiconductor substrate, and on two opposite sides of the gate structure. The source region includes at least a source doped region having the second conductive type, and at least a source contact region having the first conductive type, and the source doped region and the source contact region are alternately arranged along the first direction.