LDMOS Source Region Definition via Spacer CMP
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Solution Overview
Problem
Existing methods for fabricating LDMOS devices are limited by the capability of photo-masking equipment, which restricts the minimization of the N+/P+/N+ source/body region, hindering the reduction of the source region size and increasing manufacturing costs.
Innovation Solution
The use of spacers and chemical mechanical polishing (CMP) technology to define the N+/P+/N+ source/body region, allowing for self-aligned source and body pickup regions in a single masking step, thereby reducing the source region size and lowering production costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photo-masking equipment is used to define the N+/P+/N+ source/body region, then the manufacturing process is simple, but the source region size cannot be reduced further due to equipment capability limits
Solution Approach 1:
The patent introduces spacers as intermediary structures formed on the side walls of the polysilicon layer. These spacers serve as self-aligned masks that define the source region boundaries with precision beyond conventional photo-masking capabilities. The spacers are formed through atomic layer deposition (ALD) and anisotropic etching, creating a mediator structure that enables sub-lithographic feature sizes.
Solution Approach 2:
The patent replaces the conventional photo-masking mechanical/optical system with a spacer-based self-aligned definition system. Instead of using light exposure and photoresist patterns, the source region boundaries are defined by the physical geometry of spacers formed through sequential deposition and etching steps, achieving higher precision through material layering rather than optical projection.
2Manufacturing precision
If multiple masking steps are used to define source and body pickup regions separately, then positioning precision can be achieved, but manufacturing cost and process time increase
Solution Approach 1:
The patent merges the definition of source regions and body pickup regions into a single process sequence. The spacers formed on the polysilicon side walls simultaneously define both the source region boundaries and the body pickup region boundaries through self-alignment. This eliminates the need for separate masking steps for each region, achieving both positioning precision and manufacturing efficiency.
Solution Approach 2:
The spacers serve as self-aligned masks that automatically position the source and body pickup regions relative to the polysilicon gate structure. The self-service mechanism relies on the spacers being formed directly on the polysilicon side walls, ensuring automatic alignment without requiring additional photo-masking steps. The process self-defines the critical dimensions through the spacer thickness and formation geometry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of LDMOS devices with significantly reduced source regions and lower manufacturing costs, overcoming the limitations of conventional photo-masking techniques.
Implementation Method 1
performing chemical mechanical polishing to expose the spacers between the polysilicon block and the polysilicon layer
Implementation Method 2
etching both the block layer and the polysilicon layer, through a window of a first masking layer to expose a window to the well region
Data Source
AI summary
A method for fabricating a LDMOS device in a well region of a semiconductor substrate, including: etching a polysilicon layer above the well region through a window for a body region; and forming spacers at side walls of the polysilicon layer, to define positions of source regions in the well region.