LDMOS Gate Spacer Structure for Self-Aligned Drift Region Scaling
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Solution Overview
Problem
Lateral diffused MOS (LDMOS) transistors face issues such as excessive device size and high specific on-resistance due to the presence of field oxide, and non-self-aligned implantation can result in un-doped and un-silicide regions, limiting scaling and performance.
Innovation Solution
The proposed solution involves a self-aligned implantation process that eliminates the need for field oxide, allowing for precise control of the drift region length through the use of spacer layers, thereby reducing on-resistance and improving device scaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If field oxide is used in LDMOS transistors, then device isolation is improved, but device size increases and specific on-resistance increases
Solution Approach 1:
The patent removes the field oxide layer from the LDMOS transistor structure. By eliminating this isolating layer, the device achieves better scaling with reduced area while maintaining performance through alternative isolation methods inherent in the self-aligned implantation structure.
Solution Approach 2:
The patent transitions from planar isolation using field oxide to vertical self-aligned implantation structures. This dimensional shift allows isolation and doping control to be achieved through depth-controlled ion implantation rather than lateral field oxide extensions, reducing the overall device footprint.
2Reliability
If field oxide is used in LDMOS transistors, then device isolation is improved, but specific on-resistance increases
Solution Approach 1:
The field oxide layer is completely removed from the structure. This elimination prevents the high specific on-resistance that arises from carrier transport through or near the field oxide region, while isolation is maintained through the self-aligned implantation geometry and associated doping profiles.
Solution Approach 2:
The patent employs preliminary self-aligned implantation steps that define the drift region and doping profiles before final device formation. This preliminary doping action ensures optimal carrier concentration and mobility in the drift region, minimizing on-resistance from the outset rather than requiring field oxide for isolation.
3Ease of manufacture
If non-self-aligned implantation is used, then manufacturing flexibility is improved, but un-doped and un-silicide regions are created
Solution Approach 1:
The patent implements self-aligned implantation where the implantation mask is automatically defined by previously formed structures (such as spacers or existing doped regions). This self-alignment mechanism ensures complete and uniform doping coverage without leaving un-doped regions, while the process remains manufacturable through standard semiconductor fabrication techniques.
4Device complexity
If conventional implantation is used, then process simplicity is improved, but device scaling is limited
Solution Approach 1:
The patent utilizes precise control of ion implantation parameters (energy, dose, angle) to achieve accurate drift region length scaling. By changing these implantation parameters rather than relying on field oxide thickness or lateral dimensions, the device can be scaled to smaller dimensions while maintaining proper drift region characteristics and performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in reduced device size, lower specific on-resistance, and improved breakdown voltage, enabling better performance and scalability of LDMOS transistors.
Implementation Method 1
The drift region length is defined by the spacer thickness
Implementation Method 2
self-aligned implantation process that eliminates the need for field oxide
Data Source
AI summary
A semiconductor device includes a doped region of a first conductivity type in a substrate, a source/drain region of the first conductivity in the doped region, and a gate structure overlapping a portion of the doped region. The semiconductor device further comprises a multi-layer spacer over a first sidewall of the gate structure. The multi-layer spacer comprises a first spacer layer, a second spacer layer over the first spacer layer, and a third spacer layer over the second spacer layer. The first spacer layer and the second spacer layer are in contact with the first sidewall of the gate structure.