LDMOS Gate Spacer Horn Structure for Lower Gate-Drain Capacitance
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Solution Overview
Problem
As IC devices decrease in size, there is a need for lower power consumption and higher performance speeds, which is challenged by increased gate-drain capacitance and resistance in LDMOS transistors due to the inclusion of resist-protection oxide (RPO) and reduced silicide layers, leading to higher power consumption and heat generation.
Innovation Solution
Incorporating a horn structure on the drain side spacer that allows a silicide layer to cover the entire gate surface, reducing resistance and minimizing gate-drain capacitance and total gate charge, while maintaining a larger gate size to support the RPO, thus conserving battery power and improving switching speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If RPO is included to protect the gate, then gate protection is improved, but gate-drain capacitance and resistance increase
Solution Approach 1:
The spacer structure is designed with non-uniform thickness: thicker at the drain end and thinner at the source end. This local variation in spacer thickness allows the silicide layer to extend further toward the drain, reducing gate-drain capacitance and resistance in critical areas while maintaining gate protection where needed.
Solution Approach 2:
The invention transitions from a conventional planar structure to a three-dimensional structure by forming a spacer that extends above the gate surface. This vertical dimension allows the silicide layer to be deposited on the spacer's upper surface, creating an extended conductive path that reduces resistance and capacitance without increasing the planar footprint.
2Volume of moving object
If device size is reduced for portability, then system portability is improved, but gate-drain capacitance and resistance increase
Solution Approach 1:
By utilizing the vertical dimension through the spacer structure, the invention achieves enhanced electrical performance (lower resistance and capacitance) without increasing the horizontal device footprint, enabling size reduction while maintaining low power consumption.
Solution Approach 2:
The non-uniform spacer thickness concentrates the capacitance-reducing effect at the drain end where it is most critical, allowing the overall device to be smaller while maintaining optimal electrical characteristics in the high-stress region.
3Reliability
If silicide layer is reduced to lower resistance, then resistance is improved, but gate-drain capacitance increases
Solution Approach 1:
The silicide layer is extended onto the vertical surface of the spacer, creating an additional conductive pathway in the vertical dimension. This reduces resistance without requiring an increase in the horizontal silicide area, thereby avoiding increased gate-drain capacitance.
Data Source
AI summary
A lateral diffusion metal-oxide-semiconductor (LDMOS) transistor. includes a first gate. The LDMOS transistor further includes a first source/drain (S/D) region on a first side of the first gate. The LDMOS transistor further includes a second S/D region on a second side of the first gate, wherein the second side is opposite the first side. The LDMOS transistor further includes a first spacer surrounding the first gate. The first spacer includes a first portion on the first side of the first gate, wherein the first portion has a top surface substantially coplanar with a top surface of the first gate, and a second portion on the second side of the first gate, wherein the second portion comprises a first horn structure extending above the top surface of the first gate.