LDMOS Source Region Reduction via Spacer Self-Alignment
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Solution Overview
Problem
Existing methods for forming reduced source regions in LDMOS devices are limited by the capabilities of photo-masking equipment, restricting the miniaturization of the source/body window.
Innovation Solution
A manufacturing process using spacers to form self-aligned body and source regions in a single masking step, allowing for the creation of smaller source regions by etching through windows defined by the spacers, thereby reducing the source region size and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If photo-masking equipment is used to form source/body regions, then manufacturing process is simple, but source region size cannot be reduced below equipment capability limits
Solution Approach 1:
The patent introduces spacers as intermediary structures formed on the gate sidewalls to define the source/body region boundaries. These spacers act as a mediator between the gate structure and the source region formation, enabling precise definition of small source regions without direct photo-masking intervention at this critical dimension.
Solution Approach 2:
The source/body regions are formed through self-aligned processes where the spacers automatically position themselves relative to the gate structure. The etching process selectively removes material based on the spacer positioning, creating self-aligned regions that eliminate the need for additional photo-masking steps and achieve dimensions below conventional masking capabilities.
2Manufacturing precision
If multiple masking steps are used to form body region and source layer, then manufacturing precision is improved, but device complexity and production cost increase
Solution Approach 1:
The patent combines the formation of body region and source layer into a single integrated process step. The spacers serve as a common reference structure for both regions, allowing simultaneous definition of both doped regions in one etching and doping sequence, thereby reducing the number of separate masking steps required.
Solution Approach 2:
The spacers are formed in advance on the gate sidewalls before the source/body region definition step. This preliminary action establishes the alignment reference structure that guides subsequent material removal and doping processes, ensuring precise positioning without requiring complex real-time masking operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process enables the fabrication of LDMOS devices with significantly reduced source regions and lower production costs, overcoming the limitations of conventional photo-masking techniques.
Implementation Method 1
forming a layer of material having faster etching rate than the gate oxidation layer above the polysilicon layer; etching both of the layer of material having faster etching rate than the gate oxidation layer and the polysilicon layer through a window of a first masking layer
Implementation Method 2
implanting dopants of a second doping type into the well region under the window of the first masking layer to form a body region; implanting dopants of the first doping type into the body region under the window of the first masking layer to form a source layer
Implementation Method 3
forming a gate oxidation layer above the well region; oxidizing side walls of the polysilicon layer
Data Source
AI summary
A method for fabricating a LDMOS device in a well region of a semiconductor substrate, including: forming a body region and a source layer in the well region through a window of a polysilicon layer above the well region, wherein the body region has a deeper junction depth than the source layer; forming spacers at side walls of the polysilicon layer; and etching through the source layer through a window shaped by the spacers, wherein the source layer under the spacers is protected from etching, and is defined as source regions of the LDMOS device.