LDMOS Spacer Structure for Self-Aligned Source-Drain Scaling
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Solution Overview
Problem
Lateral diffused MOS (LDMOS) transistors face issues with excessive device size and high specific on-resistance due to field oxide (FOX) structures, and non-self-aligned implantation techniques lead to misalignment and unsilicided regions, limiting scalability and performance.
Innovation Solution
A self-aligned implantation process is implemented, omitting FOX and using spacer layers to precisely control the formation of source and drain regions, reducing un-doped and unsilicided areas and allowing for scaled-down drift regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If field oxide (FOX) structures are used in LDMOS transistors, then device isolation is improved, but device size increases and specific on-resistance becomes excessive
Solution Approach 1:
The patent removes the field oxide (FOX) structure from the LDMOS transistor design. By extracting this isolating structure, the device achieves adequate isolation through alternative means (such as junction isolation or shallow trench isolation) while significantly reducing the overall device footprint and specific on-resistance, thus resolving the contradiction between isolation reliability and device size.
2Ease of manufacture
If non-self-aligned implantation techniques are used, then manufacturing flexibility is improved, but misalignment occurs and unsilicided regions are created
Solution Approach 1:
The patent employs a self-aligned implantation technique where the implantation mask is formed after the gate structure and spacer layers are already in place. This preliminary positioning of structural elements before implantation ensures that the dopant regions are automatically aligned with the gate, eliminating misalignment issues and ensuring complete silicidation, thus resolving the contradiction between manufacturing flexibility and alignment precision.
3Device complexity
If conventional LDMOS structures are used, then device simplicity is maintained, but scalability is limited and performance metrics deteriorate
Solution Approach 1:
The patent introduces a vertical dimension to the LDMOS structure by forming spacer layers that extend vertically from the gate structure. This three-dimensional configuration allows for better control of dopant regions and improved device performance while maintaining scalability. The vertical spacers enable precise definition of source and drain regions without increasing lateral device dimensions, thus resolving the contradiction between structural simplicity and scalability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces device size, minimizes specific on-state resistance, and enhances breakdown voltage and switch speed, improving the figure of merit for LDMOS transistors.
Implementation Method 1
a first ion implantation process is performed to form a body region of a first conductivity type and a doped region of a second conductivity type in the semiconductor substrate
Data Source
AI summary
A semiconductor device includes a source region, a drain region, a gate structure, a first gate spacer, and a second gate spacer. The source region and the drain region are in a substrate. The gate structure is laterally between the source region and the drain region. The first gate spacer is on a first sidewall of the gate structure. The second gate spacer is on a second sidewall of the gate structure. The first gate spacer has more layers than the second gate spacer.