LDMOS Stair-Shaped Field Plate Layout for Breakdown-Resistance Tradeoff
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Solution Overview
Problem
Lateral double-diffused metal oxide semiconductor (LDMOS) transistors face a contradiction between achieving high off-state breakdown voltage and low on-state resistance, as the doping concentration and oxide layer thickness requirements are mutually exclusive, leading to poor performance in existing designs.
Innovation Solution
A stair-shaped field dielectric layer is formed using a salicidation block layer as a second dielectric layer and multiple contact channels as a second field plate layer, increasing the distance between the field plate layer and the silicon substrate, thereby enhancing breakdown voltage and reducing on-state resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single field plate layer with uniform oxide dielectric layer is used, then the manufacturing process is simple, but the breakdown voltage cannot be sufficiently increased and on-state resistance remains high
Solution Approach 1:
The field plate structure is segmented into multiple layers: a first field plate layer with a first dielectric layer, and a second field plate layer with a second dielectric layer. This segmentation allows each layer to contribute differently to the electric field distribution, enabling higher breakdown voltage while maintaining manageable manufacturing complexity through standardized layer deposition processes.
Solution Approach 2:
The patent transitions from a single-plane field plate structure to a multi-layer stacked structure in the vertical dimension. By adding the second field plate layer above the first field plate layer with different dielectric materials, the structure exploits the vertical dimension to create more sophisticated electric field control without significantly increasing lateral footprint, thus improving breakdown voltage without proportionally increasing device area.
2Reliability
If the oxide dielectric layer thickness is increased to improve breakdown voltage, then the off-state breakdown voltage increases, but the on-state resistance increases as well
Solution Approach 1:
Different dielectric layers are assigned different material properties and thicknesses optimized for their specific functions: the first dielectric layer (e.g., silicon oxide) provides a balance of breakdown strength and capacitance, while the second dielectric layer (e.g., silicon nitride) provides enhanced breakdown voltage with lower capacitance. This local optimization of material properties allows the structure to achieve high off-state breakdown voltage without the on-state resistance penalty that would result from uniformly increasing a single dielectric layer thickness.
Solution Approach 2:
The patent employs a composite dielectric structure combining two different dielectric materials with complementary properties. The first dielectric layer and second dielectric layer work together in series to provide superior overall breakdown voltage characteristics while maintaining appropriate capacitance levels, thereby achieving high reliability without compromising on-state performance.
Data Source
AI summary
The present disclosure relates to a lateral double-diffused transistor and a manufacturing method of the transistor. The transistor comprises: a substrate; a well region and a drift region both located in the top of the substrate, a source region located in the well region, and a drain region located in the drift region; a first dielectric layer located on a surface of the drift region; a first field plate layer located above the drift region and covering a first portion of the first dielectric layer; a second dielectric layer covering a surface of part of the first field plate layer and stacked on a surface of a second portion of the first dielectric layer; a second field plate layer located on a surface of the second dielectric layer, comprising at least one contact channel. According to the present disclosure, the transistor increases breakdown voltage and reduces on-state resistance.