Stepped Barrier Layer in LDMOS for Breakdown Without STI Resistance Penalty
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Solution Overview
Problem
Conventional LDMOS devices using Shallow Trench Isolation (STI) technology improve breakdown voltage but increase on-resistance, necessitating a solution that enhances breakdown voltage without affecting on-resistance.
Innovation Solution
The method involves forming a semiconductor substrate with a body and drift region, a source and drain region, and a gate structure, followed by depositing a first oxide layer and a barrier layer with multiple etch stop layers and insulating layers, and forming field plate holes to create a stepped barrier layer that improves breakdown voltage while reducing on-resistance by eliminating shallow trench isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If Shallow Trench Isolation (STI) technology is adopted to improve breakdown voltage, then breakdown voltage is improved, but on-resistance increases
Solution Approach 1:
The patent removes the STI structure from the device architecture. By eliminating the shallow trench isolation, the harmful increase in on-resistance is avoided while maintaining the ability to control breakdown voltage through alternative means (the stepped barrier layer structure).
Solution Approach 2:
The patent transitions from a planar STI-based isolation approach to a multi-level stepped barrier layer structure. This vertical dimensionality change allows for improved breakdown voltage control without the lateral isolation constraints that increase on-resistance in conventional STI designs.
2Strength
If a stepped barrier layer structure with multiple etch stop layers is formed, then breakdown voltage is improved through electric field distribution, but device complexity increases
Solution Approach 1:
The barrier layer is segmented into multiple etch stop layers with different etch selectivities. This segmentation enables the formation of a stepped structure that controls electric field distribution, improving breakdown voltage while allowing for selective etching processes that manage the complexity through standardized fabrication steps.
Solution Approach 2:
The patent changes the structural parameters of the barrier layer by introducing multiple etch stop layers with varying thicknesses and material compositions. This parameter variation creates the stepped configuration that optimizes breakdown voltage while the parameters are controlled within standard semiconductor manufacturing ranges.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the breakdown voltage of LDMOS devices while maintaining low on-resistance, resulting in improved performance by uniformly distributing the electric field and reducing on-resistance through the elimination of shallow trench isolation.
Implementation Method 1
uniformly distributing the electric field
Implementation Method 2
reducing on-resistance through the elimination of shallow trench isolation
Data Source
AI summary
The present invention relates to an LDMOS device and a method for preparing same. When a field plate hole is formed by etching an interlayer dielectric layer, the etching of the field plate hole is stopped on a blocking layer by means of providing the blocking layer between a semiconductor base and the interlayer dielectric layer. Since the blocking layer is provided with at least one layer of an etch stop layer, and steps are formed on the surface of the blocking layer, at least two levels of formed hole field plates are distributed in a step shape, and lower ends of the first level of hole field plates to the nth level of hole field plates are gradually further away from the drift area in the direction from a gate structure to a drain area.