LDMOS Transistor Stepped Gate Oxide Shielding
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Solution Overview
Problem
LDMOS transistors in RF power amplifiers for personal communications systems experience high Idq-degradation when scaled down, leading to reduced lifetime and performance issues.
Innovation Solution
The LDMOS transistor incorporates a stepped shield layer structure with multiple gate oxide layers of varying thicknesses to reduce hot carrier degradation, improving current capability and on-resistance while maintaining RF performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the gate length of the LDMOS transistor is reduced to reduce the area, then the area is reduced, but the Idq-degradation becomes too high
Solution Approach 1:
The patent applies local quality by creating a stepped shield layer structure where different portions of the drain extension region have different shield layer configurations. Specifically, a first portion has a shield layer with a first thickness while a second portion has a shield layer with a second thickness greater than the first. This localized differentiation allows the transistor to maintain reduced area while managing hot carrier effects and Idq-degradation in specific critical regions through enhanced shielding where needed.
2Reliability
If a shield layer with stepped structure is provided to reduce Idq-degradation, then the Idq-degradation is reduced, but the device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the drain extension region into multiple portions (first portion and second portion) with different shield layer thicknesses. This segmentation allows targeted protection against hot carrier effects in specific regions while maintaining simplicity in other areas, thus reducing Idq-degradation without uniformly increasing complexity across the entire device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces Idq-degradation by more than 5% over 20 years, enhancing the transistor's reliability and linear efficiency, and improves RF performance by minimizing feedback capacitance.
Implementation Method 1
Hot carrier degradation of the LDMOS transistor manifests itself by a drift in the quiescent current (Idq) of the LDMOS transistor
Implementation Method 2
a second gate oxide layer extending over a region where a local maximum of an electric field generates hot carriers
Data Source
Figure 1~2
Figure 3~4
Figure 5~6
AI summary
The LDMOS transistor (1) of the invention comprises a source region (3), a channel region (4), a drain extension region (7) and a gate electrode (10). The LDMOS transistor (1) further comprises a first gate oxide layer (8) and a second gate oxide layer (9), which is thicker than the first gate oxide layer (8). The first gate oxide layer (8) at least extends over a first portion of the channel region (4), which is adjacent to the source region (3). The second gate oxide layer (9) extends over a region where a local maximum (A, B) of the electric field (E) generates hot carriers thereby reducing the impact of the hot carriers and reducing the Idq-degradation. In another embodiment the second gate oxide layer (9) extends over a second portion of the channel region (4), which mutually connects the drain extension region (7) and the first portion of the channel region (4), thereby improving the linear efficiency of the LDMOS transistor (1).