LDMOS Device High Tensile Stress Isolation
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Solution Overview
Problem
Conventional LDMOS devices with shallow trench isolation (STI) technology experience an undesirable increase in on-resistance (Ron), which is critical to prevent power loss, and further improvements are needed to maintain low Ron and enhance transistor performance.
Innovation Solution
Incorporating a high tensile stress isolation region between the gate electrode and the drain region, utilizing shallow trench isolation with high stress insulating materials like silicon oxide, to induce localized stress in the substrate and reduce Ron while maintaining high saturation current and transconductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If shallow trench isolation (STI) technology is used to form field isolation regions, then device performance is improved through reduced dimensions and improved latch-up immunity, but on-resistance (Ron) increases undesirably
Solution Approach 1:
The patent changes the physical and chemical parameters of the isolation region by introducing high tensile stress through specific dielectric materials and structural configurations. This stress parameter modification reduces carrier mobility degradation and lowers on-resistance while maintaining the dimensional advantages of STI technology
Solution Approach 2:
The patent applies localized stress to specific regions of the substrate through the isolation structure. By concentrating tensile stress in the channel region beneath the gate electrode, the device achieves improved carrier mobility and reduced on-resistance in critical areas without affecting other device regions
2Length of moving object
If the gate length and off-set distance are scaled down to improve device performance, then transistor dimensions are reduced, but on-resistance increases and power loss worsens
Solution Approach 1:
The patent modifies the stress parameter in the substrate to compensate for the reduced gate length. By introducing high tensile stress through the isolation region, carrier mobility is enhanced, which offsets the increased on-resistance that would normally result from scaling down the gate length
Solution Approach 2:
The patent applies preliminary stress to the substrate before the device operates at scaled dimensions. This pre-applied tensile stress counteracts the negative effects of reduced gate length on carrier mobility, preventing the expected increase in on-resistance and power loss
3Reliability
If drain engineering techniques and strained silicon technology are employed to reduce on-resistance, then transistor gain improves, but device complexity increases
Solution Approach 1:
The patent combines the isolation region formation with stress induction functionality. The same STI structure that provides electrical isolation also serves as a stress-inducing element, eliminating the need for separate strain engineering structures and simplifying the overall device architecture
Solution Approach 2:
The isolation region is designed to perform multiple functions simultaneously: electrical field isolation, mechanical stress induction, and carrier mobility enhancement. This multi-functionality reduces device complexity by consolidating what would otherwise require separate structural elements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The high tensile stress isolation region effectively reduces on-resistance by approximately 12% and increases saturation current by 50% compared to prior art devices, without significantly affecting breakdown voltage, enabling improved performance in high-voltage, high-power applications.
Implementation Method 1
The isolation region includes a region of high tensile stress and is configured to apply localized stress in a substrate in close proximity to the drain region
Data Source
AI summary
An LDMOS device includes a substrate having a surface and a gate electrode overlying the surface and defining a channel region in the substrate below the gate electrode. A drain region is spaced apart from the channel region by an isolation region. The isolation region includes a region of high tensile stress and is configured to induce localized stress in the substrate in close proximity to the drain region. The region of high tensile stress in the isolation region can be formed by high-stress silicon oxide or high-stress silicon nitride. In a preferred embodiment, the isolation region is a shallow trench isolation region formed in the substrate intermediate to the gate electrode and the drain region.