LDMOS Stress Layer and Dummy Gate Design for Carrier Mobility
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for fabricating semiconductor devices, particularly LDMOS, face challenges in maintaining high carrier mobility as devices are scaled down, and existing stress engineering techniques are complex and costly, limiting performance enhancement.
Innovation Solution
The use of a stress layer over the substrate and gate in LDMOS devices, combined with dummy gates, to create tensile or compressive stress in the channel and junction regions, enhancing carrier mobility and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thicker nitride layers are used to achieve higher stress levels, then carrier mobility increases, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent employs a composite stress engineering approach by combining nitride stressor layers with silicon-germanium (SiGe) sacrificial layers. This composite structure allows the nitride layer to provide tensile stress for enhanced carrier mobility while the SiGe layer facilitates controlled stress distribution and relaxation, achieving high mobility without requiring excessively thick nitride layers that would increase complexity
Solution Approach 2:
The patent utilizes parameter changes by varying the thickness and composition of the SiGe sacrificial layer (e.g., 5-20 nm thickness, different Ge concentrations) to control the stress profile in the channel. By adjusting these parameters, the desired tensile stress is achieved in the silicon layer without needing to increase nitride layer thickness, thereby maintaining manufacturing simplicity
2Productivity
If device dimensions are scaled down to increase transistor density, then productivity increases, but maintaining high carrier mobility becomes more difficult
Solution Approach 1:
The patent applies local quality by introducing stress specifically in the channel region through the nitride/SiGe composite structure. The stress is localized to where it is most needed (the channel) while other regions maintain their original properties. This allows scaled-down devices to retain high carrier mobility in the critical channel area despite reduced overall dimensions and increased density
Solution Approach 2:
The patent changes physical parameters by introducing mechanical stress (strain) in the silicon channel layer through the underlying SiGe sacrificial layer. This parameter change (strain engineering) fundamentally alters carrier mobility without requiring changes to device geometry, enabling high mobility to be maintained even as device dimensions are scaled down for higher density
3Reliability
If multiple stress engineering techniques are combined to enhance performance, then device performance improves, but manufacturing process complexity increases
Solution Approach 1:
The patent merges two stress engineering techniques - nitride stressor layers and SiGe sacrificial layers - into a unified composite structure. The nitride layer provides primary tensile stress while the SiGe layer provides secondary stress control and relaxation mechanisms. This merging achieves enhanced device performance through combined effects while being integrated into a single fabrication sequence, reducing the complexity that would arise from separate, sequential stress engineering steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the on-state resistance, transconductance, and breakdown voltage of LDMOS devices, increasing carrier mobility and reducing on-state resistance, while being applicable to both N and P-type devices.
Implementation Method 1
Mechanical stress in the channel region markedly influences the performance and reliability of MOS devices
Implementation Method 2
Tensile stress may be obtained by forming a nitride etch stop to create stress (that translates to strain in the underlying silicon) in the channel of a MOS device
Data Source
AI summary
First example embodiments comprise forming a stress layer over a MOS transistor (such as a LDMOS Tx) comprised of a channel and first, second and third junction regions. The stress layer creates a stress in the channel and the second junction region of the Tx. Second example embodiments comprises forming a MOS FET and at least a dummy gate over a substrate. The MOS is comprised of a gate, channel, source, drain and offset drain. At least one dummy gate is over the offset drain. A stress layer is formed over the MOS and the dummy gate. The stress layer and the dummy gate improve the stress in the channel and offset drain region.