LDMOS Super Junction Columns for Breakdown Voltage
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Solution Overview
Problem
Conventional LDMOS devices face limitations in achieving high breakdown voltage due to potential interior damage and uneven impurity distribution caused by high-energy ion implantation, which reduces their anti-breakdown capability.
Innovation Solution
A laterally diffused metal oxide semiconductor device with a super junction structure featuring alternately arranged N-columns and P-columns, formed using two separate implantation steps with reduced energy, allowing for deeper columns and shorter high-temperature drive-in times, thereby increasing breakdown voltage and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-energy ion implantation is used to increase column depth and breakdown voltage, then breakdown voltage increases, but interior damage and uneven impurity distribution occur reducing anti-breakdown capability
Solution Approach 1:
The ion implantation process is segmented into multiple steps with different energies. First, low-energy implantation forms the initial column structure, then higher-energy implantation deepens the columns. This segmentation allows achieving deep column depth without the harmful effects of single high-energy implantation, as each step uses appropriate energy for its specific purpose.
Solution Approach 2:
The low-energy ion implantation is performed as a preliminary action to form the initial N-column and P-column structures before the high-energy implantation that deepens them. This preliminary formation creates a foundation that can withstand subsequent higher-energy processing without causing interior damage or uneven impurity distribution.
2Reliability
If column depth is increased to withstand higher breakdown voltage, then breakdown voltage increases, but high-energy ion implantation causes interior damage
Solution Approach 1:
The implantation process is divided into multiple energy stages. The first stage uses lower energy to establish uniform column structures, while subsequent stages use progressively higher energies to deepen the columns. This segmented approach maintains uniform impurity distribution throughout the column depth, avoiding the non-uniformity caused by single high-energy implantation.
3Reliability
If P/N column width is reduced to increase breakdown voltage, then breakdown voltage increases, but device complexity increases
Solution Approach 1:
The invention changes the doping concentration parameters within the columns rather than reducing column width. By optimizing the doping concentrations in N-columns and P-columns and their junction depths, the invention achieves higher breakdown voltage while maintaining simple column geometries, thus avoiding increased device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves higher breakdown voltage and cost savings by forming deeper columns with lower implantation energy, ensuring effective mutual depletion during reverse operation and enhanced forward conduction.
Implementation Method 1
conventional LDMOS device mainly features that there is a relatively long lightly doped drift region between the channel region and the drain region
Implementation Method 2
forming an epitaxial layer on the bottom-layer N-region, the bottom-layer P-region, and the buried layer by an epitaxial growth process
Implementation Method 3
performing impurity ion implantation into the epitaxial layer, and performing drive-in to form a top-layer N-region, a top-layer P-region, and a well region having a second doping type
Data Source
AI summary
A laterally diffused metal oxide semiconductor device includes: a substrate (10); a buried layer region (32) in the substrate; a well region (34) on the buried layer region (32); a gate region on the well region; a source region (41) and a drain region (43) which are located at two sides of the gate region; and a super junction structure. The source region (41) is located in the well region (34); the drain region (34) is located in the super junction structure; the gate region comprises a gate oxide layer and a gate electrode on the gate oxide layer; and the super junction structure comprises a plurality of N-columns and P-columns, wherein the N-columns and the P-columns are alternately arranged in a direction which is horizontal and is perpendicular to the direction of a connecting line between the source region and the drain region, each N-column comprises a top-layer N-region (23) and a bottom-layer N-region which are butted vertically, and each P-column comprises a top-layer P-region (24) and a bottom-layer P-region which are butted vertically.