LDMOS Super-Junction Doping for Low Gate-Drain Capacitance
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Solution Overview
Problem
LDMOS devices face a trade-off between low gate-to-drain capacitance and low source-to-drain resistance (Ron), as increasing the drift region to reduce Ron leads to higher gate-to-drain capacitance, which is undesirable for RF applications.
Innovation Solution
The semiconductor device employs a specific doping structure and ion implantation process to form a super-junction structure with alternating lateral p-n doped regions, which reduces gate-to-drain capacitance and source-to-drain resistance while maintaining high breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the drift region and gate interface are increased to reduce source-to-drain resistance, then source-to-drain resistance decreases, but gate-to-drain capacitance increases
Solution Approach 1:
The drift region is segmented into multiple alternating p-type and n-type doped regions (first doped region, second doped region, third doped region, fourth doped region, fifth doped regions) instead of a single continuous region. This segmentation creates a super-junction structure that reduces the effective capacitance while maintaining low resistance through the alternating conductivity types.
Solution Approach 2:
Different portions of the drift region are doped with different conductivity types (p-type and n-type) to create localized regions with different electrical properties. The first doped region has p-type conductivity while the second doped region has n-type conductivity, and this alternation continues, allowing each local region to contribute differently to the overall electrical characteristics.
2Ease of manufacture
If conventional CMOS fabrication processes are used to form LDMOS devices, then manufacturing cost is reduced, but achieving both low gate-to-drain capacitance and low source-to-drain resistance becomes difficult
Solution Approach 1:
The invention changes the doping parameters by introducing alternating p-type and n-type doped regions with specific conductivity types and concentration levels. The ion implantation process uses different dopants (e.g., boron for p-type, phosphorus for n-type) with controlled doses and energies to achieve the desired electrical characteristics while using standard CMOS process capabilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively achieves low gate-to-drain capacitance and low source-to-drain resistance, enhancing the maximum operating frequency and breakdown voltage of LDMOS devices for RF applications.
Implementation Method 1
An ion implantation process is performed to implant dopants of the first conductive type in the semiconductor layer exposed by the trench, thereby forming a sixth doped region
Data Source
AI summary
A semiconductor device includes a semiconductor substrate and a semiconductor layer formed thereover. A gate structure is disposed over the semiconductor layer, and a first doped region is disposed in the semiconductor layer adjacent to a first side of the gate structure. A second doped region is disposed in the semiconductor layer adjacent to a second side of the gate structure opposite to the first side. A third doped region is disposed in the first doped region. A fourth doped region is disposed in the second doped region. A plurality of fifth doped regions is disposed in the second doped region. A sixth doped region is disposed in the semiconductor layer under the first doped region. A conductive contact is formed in the third doped region and the first doped region.