LDMOS Drift Region Super-Junction Layout for Lower On-Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current high-voltage LDMOS devices face challenges in reducing on-resistance and simplifying the manufacturing process while maintaining compatibility with lateral transistors, as super-junction technology has primarily been applied to vertical discrete transistors, not effectively addressing these issues in lateral transistors.
Innovation Solution
A manufacturing method for LDMOS devices involving the formation of drift and bulk regions, ion implantation to create alternating ion implantation regions, and the use of deep trench and fin structures to expose these regions, reducing on-resistance and improving thermal stability and frequency stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If super-junction technology is applied to lateral transistors, then on-resistance is reduced, but device complexity increases
Solution Approach 1:
The drift region is segmented into multiple alternating ion implantation regions (first type and second type) arranged in sequence, creating a super-junction structure that divides the region into repeating units. This segmentation reduces on-resistance while maintaining a manageable device layout through periodic patterns rather than random distribution.
Solution Approach 2:
Different regions of the drift region are given different local properties through selective ion implantation. The first ion implantation regions and second ion implantation regions have different doping types and concentrations, creating localized electrical characteristics that collectively reduce the overall on-resistance of the device.
2Ease of manufacture
If conventional LDMOS structures are used, then manufacturing process is simple, but on-resistance remains high
Solution Approach 1:
The alternating first and second ion implantation regions are formed in advance during the manufacturing process, before final device assembly. This preliminary creation of the super-junction structure through ion implantation enables subsequent processing steps to proceed with conventional techniques, maintaining ease of manufacture while achieving reduced on-resistance.
Solution Approach 2:
The ion implantation process parameters (ion type, energy, dose, and spatial distribution) are changed to create the alternating doped regions. By controlling these parameters, the patent achieves the super-junction structure that reduces on-resistance while using established ion implantation technology that fits within conventional manufacturing workflows.
3Stability of the object's composition
If deep trench structures are formed to expose ion implantation regions, then thermal stability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from a planar structure to a three-dimensional structure by forming deep trench structures that extend vertically into the drift region. This dimensional change allows exposure of the ion implantation regions at different depths, improving thermal stability through enhanced heat dissipation pathways while the trench patterns follow regular periodic arrangements to manage manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces on-resistance and enhances thermal stability and frequency stability in LDMOS devices, making them more compatible with low-voltage CMOS circuits and improving durability and thermal resistance.
Implementation Method 1
implanting ions of a first type in a region of the drift region located between the gate structure and the drain region, so as to form, at a bottom of the drift region, first ion implantation regions
Data Source
AI summary
The present disclosure provides a lateral double-diffused metal oxide semiconductor device and a manufacturing method thereof, and an electronic apparatus. The method includes: providing a semiconductor substrate, and forming a drift region and a body region in the semiconductor substrate; forming a drain region in the drift region, forming a source region in the body region, and forming, on the body region, a gate structure extending to the drift region; implanting ions of a first type, so as to form, at a bottom of the drift region, first ion implantation regions extending along a direction from the gate structure to the drain region; forming, above the first ion implantation regions, a plurality of mutually spaced deep trench structures and fin structures between adjacent ones of the deep trench structures; and implanting ions of a second type in the deep trench structures to form second ion implantation regions.