LDMOS Thick Interlayer Dielectric Field Plates
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Solution Overview
Problem
LDMOS devices face a challenge in achieving higher breakdown voltage without significantly increasing on-state resistance, which is crucial for high-voltage applications, as the existing ILD thickness limits restrict further enhancement.
Innovation Solution
The semiconductor devices incorporate an interlayer-dielectric (ILD) region with a thickness of at least 2.5 microns, along with field plates and a substrate configuration that includes source and drain regions of a first conductivity type, a gate positioned between them, and an extended drain region with a reduced surface field, to increase breakdown voltage while maintaining low on-state resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the interlayer-dielectric (ILD) layer thickness is increased to enhance breakdown voltage, then the maximum breakdown voltage is improved, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent divides the ILD structure into multiple layers with different thicknesses: a first ILD layer with thickness of 1.5-2.0 microns and a second ILD layer with thickness of 1.0-1.5 microns. This segmentation allows the total effective thickness to reach 2.5-3.5 microns for high breakdown voltage while keeping individual layer thicknesses within standard manufacturing capabilities, thus resolving the contradiction between reliability improvement and device complexity.
2Reliability
If the drift area length is increased to increase breakdown voltage, then the maximum breakdown voltage is improved, but the on-state resistance increases
Solution Approach 1:
The patent applies different ILD thicknesses at different locations: thicker ILD (first layer 1.5-2.0 microns) in regions requiring higher voltage withstand capability and thinner ILD (second layer 1.0-1.5 microns) in regions where lower resistance is critical. This local quality differentiation allows the device to achieve high breakdown voltage without substantially increasing on-state resistance, resolving the contradiction between reliability and manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively increases the maximum breakdown voltage of LDMOS devices without substantially increasing on-state resistance, enabling the devices to handle higher voltages efficiently.
Implementation Method 1
An interlayer-dielectric (ILD) region with a thickness of at least 2.5 microns is formed over the surface and the gate of the device
Implementation Method 2
one or more field plates configured to shape an electrical field generated between the source region and the drain region when a voltage is applied to the gate
Data Source
AI summary
Semiconductor devices, such as LDMOS devices, are described that include an interlayer-dielectric layer (ILD) region having a thickness of at least two and one half (2.5) microns to increase the maximum breakdown voltage. In one or more implementations, the semiconductor devices include a substrate having a source region and a drain region formed proximate to a surface of the substrate. A gate is positioned over the surface and between the source region and the drain region. An ILD region having a thickness of at least two and one half (2.5) microns is formed over the surface and the gate of the device. The device also includes one or more field plates configured to shape an electrical field generated between the source region and the drain region when a voltage is applied to the gate.