LDMOS Device Third Doped Region Reduces On-Resistance
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Solution Overview
Problem
Lateral double-diffused metal oxide semiconductor (LDMOS) devices face challenges in achieving low on-state resistance (Ron) while maintaining high breakdown voltage and saturation current, as the formation of a field oxide layer to extend device lifetime increases Ron and decreases saturation current.
Innovation Solution
The LDMOS device design includes a first and second well with doped regions, a gate dielectric layer, and a gate conductive layer, where the third doped region has a lower dopant concentration than the second and first doped regions, and extends below the gate conductive layer, with a field oxide layer optionally covering part of the third doped region, to reduce on-state resistance and increase saturation current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a field oxide layer is formed in the drain terminal to improve device lifetime, then device reliability is improved, but on-state resistance increases and saturation current decreases
Solution Approach 1:
The patent applies local quality by creating a third doped region with lower dopant concentration specifically in the drain terminal area below the gate conductive layer. This localized doping modification reduces on-state resistance in the critical drain region without affecting other areas of the device, thereby resolving the contradiction between reliability improvement and on-state resistance control.
2Reliability
If a field oxide layer is formed in the drain terminal to improve device lifetime, then device reliability is improved, but saturation current decreases
Solution Approach 1:
The third doped region with lower dopant concentration is locally introduced in the drain terminal beneath the gate conductive layer. This localized modification enhances carrier concentration and mobility in the drain region, thereby increasing saturation current while preserving the field oxide layer's protective function for device reliability.
3Manufacturing precision
If the dopant concentration of the third doped region is reduced, then on-state resistance decreases, but breakdown voltage may be affected
Solution Approach 1:
The patent applies local quality by creating a third doped region with lower dopant concentration specifically in the drain terminal area below the gate conductive layer. This localized doping modification reduces on-state resistance in the critical drain region without affecting other areas of the device, thereby resolving the contradiction between reliability improvement and on-state resistance control.
Solution Approach 2:
The patent introduces a vertical dimension to the doping structure by placing the third doped region below the gate conductive layer in the drain terminal. This vertical positioning allows the lower dopant concentration region to reduce on-state resistance through enhanced carrier transport in the vertical field effect region, while the overall device breakdown voltage is maintained by the horizontal doping structure and field oxide layer configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces on-state resistance and increases saturation current, enhancing the operating speed of the device while maintaining adequate breakdown voltage by optimizing the dopant concentration and structure of the doped regions.
Implementation Method 1
The dopant concentration of the third doped region is lower than that of the second doped region or that of the first doped region
Implementation Method 2
reduce the on-state resistance (Ron) and increase the saturation current
Implementation Method 3
the gate dielectric layer is punched through by the hot electrons due to the high electric field and high currents in the drain terminal, affecting the life time of the device. A typical LDMOS device forms a field oxide layer in drain terminal to improve the lifetime of the device
Data Source
AI summary
A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region.