P-Channel LDMOS Transistor Vertical Breakdown via Local Doping Compensation
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Solution Overview
Problem
P-channel LDMOS transistors face challenges with high on-resistance and punch-through behavior due to n-well doping concentration, where high doping concentration improves breakdown voltage but increases complexity and cost, while low doping concentration leads to punch-through at lower voltages and high on-resistance.
Innovation Solution
A p implant region is formed in the n-well under the p-well to locally compensate n-type dopants, modifying the doping profile and increasing the vertical breakdown voltage without altering the n-well depth, thereby reducing on-resistance and improving punch-through behavior.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the n-well comprises a relatively high doping concentration, then the vertical breakdown voltage is improved, but the punch-through voltage decreases and the device breakdown voltage is limited
Solution Approach 1:
The patent applies local quality by creating a p implant region with specific doping characteristics in a localized area under the p-well. This region has a doping concentration and depth specifically tailored to compensate for excess n-type dopants only in the critical area where punch-through occurs, while maintaining high n-well doping concentration elsewhere for high vertical breakdown voltage.
Solution Approach 2:
The patent changes the doping parameters by introducing a p implant region with specific doping concentration and depth parameters. This modifies the net doping profile in the n-well under the p-well, creating an optimized doping distribution that simultaneously achieves high vertical breakdown voltage and suppresses punch-through at appropriate voltage levels.
2Reliability
If the n-well comprises a low doping concentration, then the punch-through voltage is improved, but the on-resistance increases and the device breakdown voltage is limited
Solution Approach 1:
The patent applies local quality by creating a p implant region with specific doping characteristics in a localized area under the p-well. This region has a doping concentration and depth specifically tailored to compensate for excess n-type dopants only in the critical area where punch-through occurs, while maintaining high n-well doping concentration elsewhere for high vertical breakdown voltage.
Solution Approach 2:
The patent changes the doping parameters by introducing a p implant region with specific doping concentration and depth parameters. This modifies the net doping profile in the n-well under the p-well, creating an optimized doping distribution that simultaneously achieves high vertical breakdown voltage and suppresses punch-through at appropriate voltage levels.
3Reliability
If the depth of the n-well is increased to suppress punch-through, then the punch-through behavior is improved, but the process complexity and fabrication costs increase
Solution Approach 1:
The patent applies local quality by creating a p implant region with specific doping characteristics in a localized area under the p-well. This region has a doping concentration and depth specifically tailored to compensate for excess n-type dopants only in the critical area where punch-through occurs, while maintaining high n-well doping concentration elsewhere for high vertical breakdown voltage.
Solution Approach 2:
The patent changes the doping parameters by introducing a p implant region with specific doping concentration and depth parameters. This modifies the net doping profile in the n-well under the p-well, creating an optimized doping distribution that simultaneously achieves high vertical breakdown voltage and suppresses punch-through at appropriate voltage levels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The modified doping profile enhances the vertical breakdown voltage and reduces on-resistance, improving the transistor's performance without increasing process complexity or fabrication costs.
Implementation Method 1
A p implant region is formed in the n-well under the p-well to locally compensate n-type dopants
Data Source
Figure 1
Figure 2~3
AI summary
The p-channel LDMOS transistor comprises a semiconductor substrate (1), an n well (2) of n-type conductivity in the substrate, and a p well (3) of p-type conductivity in the n well. A portion of the n well is located under the p well. A drain region (4) of p-type conductivity is arranged in the p well, and a source region (9) of p-type conductivity is arranged in the n well. A gate dielectric (7) is arranged on the substrate, and a gate electrode (8) is arranged on the gate dielectric. A body contact region (14) of n-type conductivity is arranged in the n well. A p implant region (17) is arranged in the n well under the p well in the vicinity of the p well. The p implant region locally compensates n-type dopants of the n well to reduce the doping concentration of the n well, thereby increasing the vertical breakdown voltage at the pn junction between the n well and the p well.