LDMOS Transistor Fabrication in Sub-Micron CMOS
Solution Overview
Problem
Conventional LDMOS transistors are not typically fabricated in sub-micron CMOS processes due to incompatibility with large-volume digital CMOS device production technologies, limiting their use in efficient DC to DC converters for low-power devices like laptops and cellular phones.
Innovation Solution
A method of fabricating LDMOS transistors with specific impurity regions and a gate structure that allows for precise control of doping concentrations and placement, enabling compatibility with sub-micron CMOS processes and reducing peak surface electric fields, thus improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional LDMOS transistors are fabricated using BiCMOS or BCD processes, then device performance in terms of specific on-resistance and breakdown voltage is improved, but manufacturing complexity and process incompatibility with sub-micron CMOS processes increases
Solution Approach 1:
The patent modifies doping parameters including concentration, depth, and distribution to achieve LDMOS performance within standard CMOS process capabilities. Specific implantation doses and energy levels are adjusted to create the necessary impurity profiles without requiring specialized BiCMOS or BCD process steps.
Solution Approach 2:
The fabrication process is divided into separate implantation steps for creating different impurity regions (first and second impurity regions with opposite types). This segmentation allows each region to be optimized independently while using standard CMOS process steps, avoiding the need for complex integrated processes.
2Adaptability or versatility
If LDMOS transistors are fabricated with precise impurity region control, then compatibility with sub-micron CMOS processes is improved, but manufacturing precision requirements increase
Solution Approach 1:
Gate insulator formation is performed before drain region implantation, establishing precise alignment references in advance. This preliminary structuring enables subsequent implantation steps to achieve the required precision using standard CMOS lithography and processing capabilities.
Solution Approach 2:
The gate insulator serves as an intermediary structure that defines the boundary between source and drain regions. By using this pre-formed insulator as a mask and reference, the patent achieves precise impurity region placement without requiring ultra-precise direct implantation alignment.
3Length of moving object
If device scaling is reduced to maintain performance, then device size is reduced, but hot carrier degradation increases
Solution Approach 1:
The patent creates non-uniform doping profiles with different impurity concentrations in specific local regions (source, drain, and channel areas). This local quality variation allows the channel to maintain appropriate electric field characteristics even at reduced dimensions, mitigating hot carrier effects while enabling device scaling.
Solution Approach 2:
The patent strategically places opposite-type impurity regions to create potential wells that confine carriers in beneficial ways. What could be seen as harmful杂质 are actually used to create beneficial carrier confinement and electric field distribution that reduces hot carrier degradation in scaled devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the fabrication of LDMOS transistors compatible with sub-micron CMOS processes, enhancing their performance and reducing hot carrier degradation, allowing for smaller device scaling while maintaining device lifetime.
Implementation Method 1
implanting a first impurity region, forming a gate insulator between a source region and a drain region of the transistor... and implanting, into the drain region of the transistor, a second impurity region
Data Source
AI summary
An LDMOS transistor includes a gate including a conductive material over an insulator material, a source including a first impurity region and a second impurity region, a third impurity region, and a drain including a fourth impurity region and a fifth impurity region. The first impurity region is of a first type, and the second impurity region is of an opposite second type. The third impurity region extends from the source region under the gate and is of the first type. The fourth impurity region is of the second type, the fifth impurity region is of the second type, and the fourth impurity region impinges the third impurity region.