LDMOS Transistor Gate Oxide Rupture Prevention via Isolation Trench
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Solution Overview
Problem
Lateral double-diffused metal oxide semiconductor (LDMOS) transistors face issues with gate oxide rupture during operation, leading to device breakdown, primarily due to the activation of parasitic NPN bipolar transistors during transient modes, which is not effectively addressed by existing robust device architectures.
Innovation Solution
The proposed solution involves modifying the LDMOS transistor structure by incorporating a buried p-doped region in a p-well under the source and backgate to reduce the gain of the parasitic NPN transistor and using a vertical trench to physically isolate the parasitic NPN transistor region from the extended drain region, thereby reducing the likelihood of gate oxide rupture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the LDMOS transistor uses a conventional structure without isolation, then the device complexity is low, but gate oxide rupture occurs during operation due to parasitic NPN transistor activation
Solution Approach 1:
The device is divided into two separate regions: a first region for the extended drain where hole current is generated, and a second region for the parasitic NPN transistor. These regions are physically isolated by a vertical trench, preventing the harmful coupling between hole current and parasitic transistor activation, thereby resolving the gate oxide rupture issue without excessive complexity
Solution Approach 2:
The parasitic NPN transistor region is extracted and physically separated from the extended drain region using a vertical trench. This extraction removes the harmful interaction pathway where hole current could activate the parasitic transistor and cause gate oxide rupture, improving reliability while maintaining reasonable device complexity
2Reliability
If the gain of the parasitic NPN transistor is reduced by adding a buried p-doped layer, then the robustness improves, but the device complexity increases
Solution Approach 1:
A buried p-doped layer is added locally in the second region under the parasitic NPN transistor. This localized doping modification reduces the gain of the parasitic transistor specifically where needed, without affecting the overall device structure significantly, thereby improving robustness during transient operation with minimal increase in complexity
Solution Approach 2:
The doping concentration and distribution are modified by adding a buried p-doped layer in the second region. This parameter change reduces the parasitic NPN transistor gain, preventing excessive current amplification during transient modes and improving reliability while maintaining a relatively simple device structure
Data Source
AI summary
A modified structure of an n-channel lateral double-diffused metal oxide semiconductor (LDMOS) transistor is provided to suppress the rupturing of the gate-oxide which can occur during the operation of the LDMOS transistor. The LDMOS transistor comprises a dielectric isolation structure which physically isolates the region comprising a parasitic NPN transistor from the region generating a hole current due to weak-impact ionization, e.g., the extended drain region of the LDMOS transistor. According to an embodiment of the disclosure, this can be achieved using a vertical trench between the two regions. Further embodiments are also proposed to enable a reduction in the gain of the parasitic NPN transistor and in the backgate resistance in order to further improve the robustness of the LDMOS transistor.