LDMOS Transistor P-Type Regions for Hole Extraction
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Solution Overview
Problem
LDMOS transistors face challenges in maintaining high on-breakdown voltage and negative input breakdown voltage, particularly as the gate width increases, due to limitations in existing structures that lead to reduced breakdown voltages and inefficient hole current paths.
Innovation Solution
The semiconductor device incorporates a p-type semiconductor region PISO provided over the n-type buried region and a p-type semiconductor region H1PW, which partially overlap and are positioned to reduce the resistance and length of hole current paths, enhancing breakdown voltages by creating additional paths for hole extraction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the gate width is increased, then the current carrying capacity is improved, but the on-breakdown voltage is decreased
Solution Approach 1:
The invention divides the semiconductor substrate into multiple isolated regions, each containing an LDMOS transistor. This segmentation allows each transistor to maintain high on-breakdown voltage while the overall device achieves high current carrying capacity through parallel operation of multiple transistors.
Solution Approach 2:
The invention introduces a buried semiconductor region as an intermediary structure between the deep well and the drift region. This buried region provides additional hole extraction paths that prevent snap-back phenomenon and maintain high on-breakdown voltage even when gate width is increased for higher current capacity.
2Ease of manufacture
If conventional LDMOS structures are used, then manufacturing is simplified, but negative input breakdown voltage is insufficient
Solution Approach 1:
The invention embeds a buried semiconductor region within the existing deep well structure, creating a nested configuration. This approach maintains manufacturing simplicity by using standard isolation techniques while adding the functional benefit of improved negative input breakdown voltage through the embedded region.
Data Source
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AI summary
A first p type semiconductor region is provided between an n type drift region surrounding a drain region and an n type buried region, and a second p type semiconductor region is provided between the first p type semiconductor region and a p type well region surrounding a source region so as to overlap the first p type semiconductor region and the p type well region. Negative input breakdown voltage can be ensured by providing the first p type semiconductor region over the n type buried region. Further, potential difference between the source region and the first p type semiconductor region can be increased and the hole extraction can be performed quickly. Also, a path of hole current flowing via the second p type semiconductor region can be ensured by providing the second p type semiconductor region. Thus, the on-breakdown voltage can be improved.