LDMOS Transistor Recessed Gate Reduces Rdson
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Solution Overview
Problem
Conventional Lateral Double-Diffused (LD) transistors are susceptible to hot carrier injection (HCI) degradation, leading to increased drain-to-source on-resistance (Rdson) and reduced switching speeds, which compromises device reliability.
Innovation Solution
The formation of a high voltage device with a recessed region in the substrate, where the transistor gate is positioned over the recessed surface, and source and drain regions are formed with underlapping device wells, reducing hot carrier trapping and enhancing carrier mobility by shifting substrate current through the bulk of the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional LD transistor structure is used, then device reliability is compromised due to hot carrier injection degradation, but device complexity remains simple
Solution Approach 1:
The patent introduces a recessed region that extends vertically into the substrate, creating a three-dimensional structure. The gate is positioned over the recessed surface, and the source/drain regions are formed with underlapping device wells that extend into the substrate. This vertical dimensionality change shifts the substrate current path through the bulk of the substrate, away from the silicon-silicon oxide interface, thereby reducing hot carrier trapping and improving device reliability without excessive complexity increase
Solution Approach 2:
The patent segments the substrate into distinct regions: a recessed region containing the transistor structure and device regions surrounding it. The device wells are segmented to underlap the recessed region, creating separate zones for current flow and field control. This segmentation allows the substrate current to flow through the bulk substrate rather than along the interface, reducing HCI degradation
2Speed
If techniques are employed to reduce Rdson in conventional LD transistors, then switching speeds improve, but hot carrier injection degradation increases
Solution Approach 1:
By creating a recessed region and positioning the gate over the recessed surface with underlapping device wells, the patent establishes a vertical current path through the bulk substrate. This three-dimensional configuration enables lower Rdson for improved switching speeds while simultaneously directing substrate current away from the vulnerable silicon-silicon oxide interface, reducing hot carrier injection degradation and maintaining device reliability
3Productivity
If substrate current flows along the silicon and silicon oxide interface, then device operation is enabled, but hot carrier trapping occurs leading to increased Rdson
Solution Approach 1:
The recessed region structure with underlapping device wells redirects the substrate current path from the horizontal interface flow to a vertical path through the bulk substrate. This dimensional change maintains device operation by enabling current flow while eliminating the interface proximity that causes hot carrier trapping and energy loss, thereby reducing Rdson
Data Source
AI summary
High voltage devices and methods for forming a high voltage device are disclosed. The method includes providing a substrate having top and bottom surfaces. The substrate is defined with a device region and a recessed region disposed within the device region. The recessed region includes a recessed surface disposed lower than the top surface of the substrate. A transistor is formed over the substrate. Forming the transistor includes forming a gate at least over the recessed surface and forming a source region adjacent to a first side of the gate below the recessed surface. Forming the transistor also includes forming a drain region displaced away from a second side of the gate. First and second device wells are formed in the substrate within the device region. The first device well encompasses the drain region and the second device well encompasses the source region.