LDMOS Transistor Shield Elements Reduce Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor transistors face challenges with increased input capacitance and feedback capacitance, which affect reliability and performance, particularly in high-frequency applications like RF power amplifiers.
Innovation Solution
A laterally diffused metal oxide semiconductor (LDMOS) transistor design incorporating two electrically conductive shield elements, one beside the gate electrode and the other spaced apart vertically, reduces hot carrier injection and feedback capacitance while maintaining low input capacitance, thereby enhancing reliability and gain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a first ground shield and a second ground shield are provided for reducing parasitic capacitance, then parasitic capacitance between drain and gate is reduced, but input capacitance increases
Solution Approach 1:
The patent transitions from conventional planar shield arrangements to a three-dimensional configuration where shield elements are positioned at different vertical levels relative to the gate electrode. The first shield element is positioned at a first vertical level and the second shield element at a second vertical level, creating spatial separation that reduces parasitic capacitance while controlling input capacitance through careful geometric design.
Solution Approach 2:
The shielding function is divided into multiple discrete shield elements positioned at different locations and vertical levels around the gate electrode. Rather than using a single continuous shield, the patent segments the shielding into multiple elements that can independently control electric field distribution, allowing optimization of both parasitic capacitance reduction and input capacitance management.
2Object-affected harmful factors
If a shield electrode is placed on the gate oxide to reduce gate-drain capacitance, then feedback capacitance is reduced, but input capacitance is adversely affected
Solution Approach 1:
The patent introduces conductive shield elements as intermediary structures positioned between the gate electrode and the drain region. These shield elements act as mediators that redirect electric field lines and reduce direct coupling between gate and drain, thereby reducing feedback capacitance while their strategic positioning minimizes their impact on input capacitance.
3Reliability
If shield elements are added to reduce parasitic capacitance, then reliability is improved, but device complexity increases
Solution Approach 1:
The shield elements are designed to serve multiple functions simultaneously: they reduce parasitic capacitance between gate and drain, control electric field distribution to minimize hot carrier injection, and are positioned to have minimal impact on input capacitance. This multi-functionality allows the patent to improve reliability through a single design modification rather than adding separate structures for each problem.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces input capacitance by 10% and feedback capacitance by 40%, improving the transistor's performance and reliability in high-frequency applications without significantly increasing input capacitance, thus enhancing the overall gain and stability.
Implementation Method 1
a gate electrode configured to provide an electric field for influencing the channel region
Implementation Method 2
a first electrically conductive shield element extending in a horizontal direction parallel to a main surface of the semiconductor substrate and being arranged beside the gate electrode spaced apart from the drain extension region
Data Source
AI summary
It is disclosed a semiconductor transistor, comprising a semiconductor substrate (111) in which a channel region (115) and a drain extension region (119) connected to the channel region are provided; a gate electrode (127) configured to provide an electric field for influencing the channel region; a first electrically conductive shield element (131) extending in a horizontal direction (103) parallel to a main surface of the semiconductor substrate and being arranged beside the gate electrode spaced apart from the drain extension region in a vertical direction (105) perpendicular to the horizontal direction; and a second electrically conductive shield element (133) arranged spaced apart from the first shield element in the vertical direction, wherein the gate electrode protrudes over the first shield element in the vertical direction.