LDMOS Device Trench Conductive Layer Reduces On-State Resistance
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Solution Overview
Problem
Conventional LDMOS devices require high-temperature thermal diffusion and high-energy ion implantation for forming the P+ type doped region, leading to increased on-state resistance and device size, which is costly and unfavorable for further miniaturization and cost reduction.
Innovation Solution
The proposed LDMOS device fabricates a semiconductor substrate with conductive trenches and layers to reduce the distance between the gate and doped regions, eliminating the need for high-energy ion implantation and thermal diffusion, thereby minimizing on-state resistance and device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-energy ion implantation and high-temperature thermal diffusion are used to form the P+ type doped region, then the device performance is improved, but the on-state resistance increases and device size increases
Solution Approach 1:
The patent changes the formation method of the P+ type doped region from high-energy ion implantation and high-temperature thermal diffusion to a lower-energy process. This parameter change in the manufacturing process reduces the diffusion depth and lateral spread of dopants, thereby reducing the required distance between the gate and doped region, which directly reduces device size while maintaining performance
Solution Approach 2:
The patent introduces a conductive layer in a trench structure below the substrate, creating a new dimensional pathway for current flow. This vertical dimensionality change allows current to bypass the high-resistance path through the substrate, reducing on-state resistance without requiring larger lateral dimensions
2Reliability
If high-energy ion implantation and high-temperature thermal diffusion are used to form the P+ type doped region, then the device performance is improved, but the fabrication cost increases
Solution Approach 1:
The patent changes the energy parameters of the ion implantation process to lower levels, which reduces the complexity and cost of the fabrication equipment and process control required. Lower energy implantation is a more成熟 and cost-effective technology compared to high-energy processes
Solution Approach 2:
The patent uses a conductive layer in a trench that can be formed using standard, cost-effective deposition and etching processes. This structure replaces the need for expensive high-energy ion implantation and high-temperature thermal diffusion equipment, utilizing more economical fabrication techniques
3Reliability
If a predetermined distance is kept between the gate structure and the N+ type doped region to ensure good performance, then the device performance is improved, but the on-state resistance increases
Solution Approach 1:
The patent introduces a vertical current path through the conductive layer in the trench, allowing current to flow downward and bypass the lateral path through the high-resistance region. This dimensional change in current flow path eliminates the trade-off between distance and resistance
Solution Approach 2:
The conductive layer in the trench acts as an intermediary current path between the source and drain regions. It provides a low-resistance shunt that mediates the current flow, allowing the gate-to-doped-region distance to be reduced without increasing on-state resistance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a reduced size and fabrication cost for LDMOS devices while preventing inductor coupling and cross-talk, with improved performance by reducing the on-state resistance and eliminating the need for high-energy processing steps.
Implementation Method 1
currents (not shown) from the drain side (e.g. N+ type doped region 108) laterally flow through a channel (not shown) underlying the gate structure G towards a source side (e.g. N+ type doped region 110), and are then guided by the P− type doped region 104 and the P+ type doped region 120
Implementation Method 2
formation of the P+ type doped region 120 needs to perform ion implantations of high doping concentrations and high doping energies
Implementation Method 3
thermal diffusion processes with a relatively high temperature above about 900° C.
Data Source
AI summary
A LDMOS device includes a substrate having opposite first and second surfaces; a well region in a portion of the substrate; a gate structure over a portion of the substrate; a first doped region disposed in a portion of the well region from a first side; a second doped region disposed in the well region from a second side; a third doped region disposed in the first doped region; a fourth doped region disposed in the second doped region; a first trench in the third doped region, the first doped region, the well region, and the substrate adjacent to the first surface; a conductive contact in the first trench; a second trench in the substrate adjacent to the second surface; a first conductive layer in second trench; and a second conductive layer over the second surface of the substrate and the first conductive layer.