LDMOS Trench Crystal Orientation for Stable On-Resistance

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Solution Overview

Problem

Conventional semiconductor devices with lateral double-diffused MOS (LDMOS) structures face variability in trench inner angles due to dry etching methods, leading to inconsistent device characteristics.

Innovation Solution

The semiconductor device employs a wet etching method to form trenches with specific crystal plane orientations, such as (111) for side surfaces and (100) for bottom surfaces, to stabilize trench geometry and improve device characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If dry etching method is used to form trenches, then manufacturing process is well-established, but trench inner angle varies depending on conditions such as trench size and pattern density, leading to inconsistent device characteristics

Engineering Contradiction:
Improvetrench inner angle consistencyVSAvoiddevice characteristic consistency
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent changes the etching method parameter from dry etching to wet etching. This parameter change fundamentally alters the etching mechanism, allowing the trench inner angle to be determined by the crystal orientation of the semiconductor substrate rather than by process conditions, thereby achieving consistent device characteristics

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent replaces the physical/mechanical dry etching process with a chemical wet etching process. This substitution allows the etching rate to be determined by crystal orientation, making the trench geometry independent of pattern density and other variable conditions

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Reliability

If wet etching method is used to form trenches with specific crystal plane orientations, then trench geometry is stabilized and device characteristics are improved, but manufacturing process complexity increases

Engineering Contradiction:
Improvedevice characteristic consistencyVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by creating different crystal plane orientations at different locations within the trench structure. The side surfaces expose (111) planes while the bottom surface exposes (100) planes, achieving both trench angle stabilization and reduced impact ionization at specific locations

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces on-resistance between the source and drain regions by minimizing impact ionization at trench corners, thereby enhancing the overall performance and reliability of the semiconductor device.

Implementation Method 1

The first trench has a first side surface facing the source region in a first direction extending from one of the source region and the drain region to the other and a first bottom surface which is connected to the first side surface and is along the main surface of the semiconductor substrate. A crystal plane of a first surface of the semiconductor substrate, which is the first side surface of the first trench, is a (111) plane. A crystal plane of a second surface of the semiconductor substrate, which is the bottom surface of the first trench, is a (100) plane.

Methodology Applied
Scientific EffectWet etching:

Implementation Method 2

This approach reduces on-resistance between the source and drain regions by minimizing impact ionization at trench corners

Methodology Applied
Scientific EffectImpact ionization:

Data Source

PatentUS12266727B2Semiconductor device and method of manufacturing the same
Publication Date: 2025.04.01 RENESAS ELECTRONICS CORP
  • US12266727B2 patent drawing
  • US12266727B2 patent drawing
  • US12266727B2 patent drawing

AI summary

The source region, drain region, buried insulating film, gate insulating film, and gate electrode of the semiconductor device are formed in a main surface of a semiconductor substrate. The buried insulating film is buried in a first trench formed between the source and drain regions. The first trench has a first side surface and a first bottom surface. The first side surface faces the source region in a first direction extending from one of the source and drain regions to the other. The first bottom surface is connected to the first side surface and is along the main surface of the semiconductor substrate. A crystal plane of a first surface of the semiconductor substrate, which is the first side surface of the first trench, is (111) plane. A crystal plane of a second surface of the semiconductor substrate, which is the bottom surface of the first trench, is (100) plane.