LDMOS Device Trench Dielectric Parasitic Capacitance
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Solution Overview
Problem
Existing LDMOS semiconductor devices face challenges in minimizing parasitic capacitance, particularly gate-to-drain capacitance, which leads to power losses during high-frequency switching operations, and existing solutions either compromise on pitch or breakdown voltage.
Innovation Solution
The LDMOS semiconductor device incorporates a trench dielectric structure with a first trench conductive region electrically connected to the body and source regions, reducing electrical field generation and hot-carrier injection, while maintaining a low on-state resistance and minimizing parasitic capacitance through a superjunction design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a conductive shield is extended over the gate terminal and LDD region to reduce parasitic capacitance, then gate-to-drain capacitance is reduced, but the minimum pitch is constrained and breakdown voltage drops considerably
Solution Approach 1:
The patent transitions from a planar conductive shield structure to a three-dimensional configuration where the drain region extends vertically through the substrate. This vertical extension allows the drain to be positioned beneath the gate without requiring lateral spacing, thereby reducing parasitic capacitance while maintaining adequate breakdown voltage through the vertical junction depth rather than lateral separation.
Solution Approach 2:
Instead of extending the conductive shield laterally over the gate and LDD region as in conventional designs, the patent inverts the approach by extending the drain region vertically downward through the substrate beneath the gate. This inverted geometry achieves field decoupling through vertical separation rather than lateral shielding, resolving the contradiction between capacitance reduction and breakdown voltage maintenance.
2Productivity
If the pitch of the base cell is reduced to improve device integration, then productivity increases, but parasitic capacitance minimization becomes more difficult
Solution Approach 1:
The patent resolves the pitch-capacitance contradiction by moving the field decoupling mechanism from the lateral plane to the vertical dimension. The drain region extending through the substrate creates vertical separation between gate and drain fields, allowing lateral pitch to be minimized for high integration while parasitic capacitance remains low due to the vertical field isolation.
3Reliability
If a conductive shield is used to attenuate hot-carrier injection, then reliability improves, but device complexity increases
Solution Approach 1:
The patent extracts the hot-carrier injection protection function from the separate conductive shield structure and integrates it into the drain region itself. By extending the drain vertically through the substrate beneath the gate, the structure inherently provides field decoupling and hot-carrier protection without requiring additional shield layers or complex multi-layer conductive structures.
Solution Approach 2:
The patent merges multiple functions into the single vertical drain structure: it serves as the current conduction path, the field decoupling element, and the hot-carrier injection protection mechanism. This consolidation eliminates the need for separate conductive shields and reduces overall device complexity while maintaining reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively decouples the gate from the drain, reducing parasitic capacitance and power losses, achieving a balance between low on-state resistance and high breakdown voltage, with negligible hot-carrier injection and optimized pitch.
Implementation Method 1
reducing electrical field generation and hot-carrier injection
Implementation Method 2
reducing electrical field generation and hot-carrier injection
Data Source
AI summary
Methods are directed to forming an electronic semiconductor device that includes a body having a first side and a second side opposite to one another and including a first structural region facing the second side, and a second structural region extending over the first structural region and facing the first side. A body region extends in the second structural region at the first side. A source region extends inside the body region and a lightly-doped drain region faces the first side of the body. A gate electrode is formed over the body region. A trench dielectric region extends through the second structural region in a first trench conductive region immediately adjacent to the trench dielectric region. A second trench conductive region is in electrical contact with the body region and source region. An electrical contact on the body is in electrical contact with the drain region through the first structural region.