LDMOS Transistor Trench Gate Segmentation for Low On-Resistance
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Solution Overview
Problem
Conventional LDMOS transistors face challenges in achieving low on-resistance and high breakdown voltage simultaneously, which is crucial for high-frequency and power applications.
Innovation Solution
The development of LDMOS transistors with multiple gate conductors and trench structures, where one or more gate structures are partially formed in a trench, promotes low on-resistance and high breakdown voltage by optimizing dopant concentrations and gate dielectric layers, allowing for efficient current flow and enhanced voltage handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional LDMOS transistor structure with single gate is used, then manufacturing is simple, but on-resistance is high and breakdown voltage is limited
Solution Approach 1:
The gate structure is divided into multiple segments (first gate and second gate) with different functions. The first gate controls the channel formation while the second gate controls the depletion region, allowing independent optimization of on-resistance and breakdown voltage without requiring a completely new complex structure
Solution Approach 2:
The invention introduces a vertical dimension by forming the second gate in a trench structure that extends into the semiconductor substrate. This vertical placement allows the second gate to control the depletion region beneath the first gate, adding a new dimension of control that improves breakdown voltage without significantly increasing lateral device footprint
2Productivity
If multiple gate conductors and trench structures are added, then on-resistance reduces and breakdown voltage increases, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is segmented into standard steps (trench formation, dielectric deposition, gate conductor formation) that can be integrated into existing CMOS fabrication lines. Each segment corresponds to a specific function, making the complex structure manufacturable through systematic, modular processing steps rather than requiring entirely new manufacturing capabilities
Solution Approach 2:
The dielectric layer serves as an intermediary between the first gate and second gate, and also between the gate structures and the semiconductor substrate. This intermediary layer simplifies manufacturing by providing a standard deposition step that isolates and protects underlying structures while enabling the formation of subsequent gate conductors in the trench
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces on-resistance while maintaining high breakdown voltage, making the transistors suitable for high-frequency and power applications with improved performance and efficiency.
Implementation Method 1
A positive voltage VGS applied between gate electrode 116 and source electrode 104 creates negative charges in silicon semiconductor structure 102 under silicon dioxide layer 118, causing a minority-carrier channel to form
Implementation Method 2
This channel has excess electrons and will therefore conduct electric current. Consequentially, current will flow in the lateral 138 direction through silicon semiconductor structure 102 from drain n+ region 132 to source n+ region 130
Implementation Method 3
When positive voltage VDS is applied across drain electrode 108 and source electrode 104, a p-n junction at the interface of n-well 124 and p-body 126 is reversed biased. Consequentially, essentially no current flows from drain electrode 108 to source electrode 104 by default
Data Source
AI summary
A lateral double-diffused metal-oxide-semiconductor field effect (LDMOS) transistor includes a silicon semiconductor structure, a dielectric layer at least partially disposed in a trench of the silicon semiconductor structure in a thickness direction, and a gate conductor embedded in the dielectric layer and extending into the trench in the thickness direction. The dielectric layer and the gate conductor are at least substantially symmetric with respect to a center axis of the trench extending in the thickness direction, as seen when the LDMOS transistor is viewed cross-sectionally in a direction orthogonal to the lateral and thickness directions.