LDMOS Transistor Trench Gate Shield Low On-Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing LDMOS transistors face challenges in achieving low on-resistance and minimized Gate-to-Drain capacitance, which limits their current handling capability and manufacturability due to thick epitaxial layers and P+ substrates, leading to de-biasing effects and complex manufacturing processes.
Innovation Solution
The design incorporates a doped substrate with a thin epitaxial layer, a continuous conductive layer for source and gate shield, and a trench structure to enhance current flow and reduce resistance, allowing for large vertical current handling and simplified manufacturing by forming elements from a single conductive layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If thick epitaxial layers and P+ substrates are used to achieve high breakdown voltage, then breakdown voltage is improved, but on-resistance increases
Solution Approach 1:
The patent changes the substrate doping type from P+ to N+, and adjusts the epitaxial layer thickness to 2-5 micrometers with specific doping concentrations (1E16 to 1E18 atoms/cm³). These parameter changes enable achieving both high breakdown voltage (>60V) and low on-resistance by optimizing the electrical characteristics of the semiconductor layers.
Solution Approach 2:
The patent employs a composite structure consisting of an N+ substrate, lightly doped epitaxial layer, source/drain regions with different doping concentrations, and insulating layers. This composite material structure allows different regions to contribute differently to breakdown voltage and on-resistance, achieving both high voltage capability and low resistance simultaneously.
2Reliability
If stripe layout of drain electrode is used to minimize parasitic source inductance, then parasitic inductance is reduced, but current handling capability is limited due to de-biasing effect
Solution Approach 1:
The patent transitions from a planar stripe layout to a three-dimensional structure by forming source and drain electrodes that extend through insulating layers and make contact with semiconductor regions at different vertical levels. This vertical dimensionality change eliminates the de-biasing effect while maintaining low parasitic inductance.
Solution Approach 2:
The patent divides the drain electrode into multiple segments (first drain electrode contacting first drain region, second drain electrode contacting second drain region) separated by insulating layers. This segmentation allows current to flow through multiple parallel paths, increasing current handling capability while maintaining low inductance.
3Reliability
If shield gate is laterally constrained between gate and drain electrodes, then gate-to-drain capacitance is reduced, but device complexity increases
Solution Approach 1:
The patent merges the shield gate function with the existing gate structure by forming the shield gate as an extension of the gate electrode over the insulating layer. This unified structure reduces gate-to-drain capacitance without requiring separate laterally constrained shield gate components, thereby simplifying the device structure.
4Manufacturing precision
If multiple separate conductive layers are used for source contact and gate shield, then manufacturing precision can be controlled, but manufacturing process complexity increases
Solution Approach 1:
The patent combines the source contact and gate shield into a single continuous conductive layer that forms both structures simultaneously. This merging reduces the number of deposition and patterning steps required, simplifying the manufacturing process while maintaining precise alignment through a single-layer formation approach.
Data Source
AI summary
A LDMOS transistor comprises a trench formed through the epitaxial layer at least to the top surface of the substrate, the trench having a bottom surface and a sidewall contacting the source region and the portion of the channel region extending under the source region. A first insulating layer is formed over the upper surface and sidewall surfaces of the conductive gate. A continuous layer of conductive material forming a source contact and a gate shield electrode is formed along the bottom surface and the sidewall of the trench and over the first insulating layer to cover the top and sidewall surfaces of the conductive gate. A second insulating layer is formed over an active area of the transistor, including over the continuous layer of conductive material and filling the trench. A drain electrode can extend over the second insulating layer to substantially cover the active area.