LDMOS Device Trench Gate Structure
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Solution Overview
Problem
Conventional LDMOS devices require high-temperature thermal diffusion and high-energy ion implantation for doping, leading to increased on-state resistance and device size, which are costly and unfavorable for further reduction in fabrication cost and dimensions.
Innovation Solution
The proposed LDMOS device incorporates a trench formation and ion implantation process to reduce the distance between the gate and drain regions, using a conductive layer and diffused region to minimize the need for high-energy doping, thereby reducing on-state resistance and device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature thermal diffusion and high-energy ion implantation are used for doping, then the doping process can be completed, but the on-state resistance increases and device size increases
Solution Approach 1:
The patent divides the doped region into multiple segments with different doping concentrations and types. Specifically, it creates a first doped region with first conductivity type and a second doped region with second conductivity type, where the second doped region has higher doping concentration. This segmentation allows achieving complete doping and desired electrical characteristics without requiring excessively high energy implantation, thereby reducing device size while maintaining reliability.
Solution Approach 2:
The patent applies different doping concentrations and types at different locations within the semiconductor device. The second doped region adjacent to the gate structure has higher doping concentration compared to the first doped region. This local quality variation optimizes the electrical characteristics locally near the gate while controlling overall device dimensions, resolving the contradiction between doping completeness and device size.
2Reliability
If high-temperature thermal diffusion is used for doping, then the doping process can be completed, but the fabrication cost increases
Solution Approach 1:
The patent changes the doping parameters by implementing a multi-stage doping process with varying concentrations and types. Instead of using uniform high-temperature thermal diffusion throughout, it employs ion implantation with controlled energies followed by selective thermal diffusion. This parameter optimization achieves complete doping at lower overall temperature requirements, reducing fabrication costs while maintaining doping effectiveness.
3Reliability
If a predetermined distance is kept between the gate structure and the doped region, then good device performance is ensured, but the device dimensions increase
Solution Approach 1:
The patent uses local quality variation by creating a second doped region with higher doping concentration adjacent to the gate structure. This high-concentration region ensures good device performance and electrical characteristics right at the critical interface, allowing the gate structure to be positioned closer to the doped region without compromising performance, thereby reducing overall device dimensions.
Solution Approach 2:
The patent performs preliminary ion implantation to create the second doped region with high doping concentration before forming the gate structure. This preliminary action ensures that when the gate is formed closer to the doped region, the necessary electrical characteristics are already in place, allowing reduced device dimensions while maintaining performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the on-state resistance and fabrication cost while maintaining performance by eliminating the need for high-energy doping and allowing for a smaller device size, thus enhancing the efficiency and cost-effectiveness of the LDMOS device.
Implementation Method 1
perform ion implantations of high doping concentrations and high doping energies
Implementation Method 2
thermal diffusion processes with a relative high temperature above of about 900° C.
Data Source
AI summary
An LDMOS device includes: a semiconductor layer formed over a semiconductor substrate; a gate structure disposed over the semiconductor layer; a first doped region disposed in the semiconductor layer adjacent to a first side of the gate structure; a second doped region disposed in the semiconductor layer adjacent to a second side of the gate structure; a third doped region disposed in the first doped region; a fourth doped region disposed in the second doped region; a trench formed in the third doped region, the first doped region and the semiconductor layer under in the first doped region; an insulating layer covering the third doped region, the gate structure, and the fourth doped region; a conductive layer conformably formed over a bottom surface and sidewalls of the trench; a dielectric layer disposed in the trench; and a diffused region disposed in the semiconductor layer under the trench.