LDMOS Transistor TSV Source Routing for Low Resistance
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Solution Overview
Problem
Lateral double-diffused metal oxide semiconductor (LDMOS) transistors face challenges in routing the source to the substrate without increasing resistance, which is essential for high voltage and frequency operations, especially when trying to make the device vertical for better packaging options.
Innovation Solution
The formation of through semiconductor vias (TSV) with electrically conductive plugs that connect the gate, source, and drain regions, along with a contact trench that shorts the source region to the body region, reduces source resistance by providing a path for electrons to flow efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the source is routed to the bottom of the die for vertical configuration, then packaging options are improved and inductance is reduced, but source resistance increases significantly
Solution Approach 1:
The source region is segmented into multiple parts: a first source region at the bottom of the die and a second source region at the top, connected through conductive vias. This segmentation allows the source to be routed to the bottom for improved packaging while maintaining low resistance through multiple parallel conduction paths.
Solution Approach 2:
The source connection is extended from a single-plane configuration to a three-dimensional structure using vertical conductive vias that pass through the substrate. This dimensional transition enables the source to be accessed at both the bottom and top surfaces, simultaneously achieving low inductance and low resistance.
2Reliability
If the N drift region length is increased to increase breakdown voltage, then high voltage capability is improved, but device area increases
Solution Approach 1:
The source connection utilizes the vertical dimension by routing conductive paths through the substrate thickness, enabling low-resistance connection without increasing the lateral footprint of the device. This allows the drift region to be optimized for breakdown voltage without area penalty.
Solution Approach 2:
The conductive plugs in the vias are positioned strategically to provide localized low-resistance paths specifically for the source connection, while the drift region maintains its optimized length for breakdown voltage. Each region is optimized for its specific function without compromising the other.
3Reliability
If through semiconductor vias with conductive plugs are added to reduce source resistance, then source resistance is reduced, but device complexity increases
Solution Approach 1:
The conductive vias serve multiple functions: they provide mechanical support for the substrate, establish electrical connections for the source region, and enable the vertical packaging configuration. This multi-functionality reduces the need for separate structures and simplifies the overall device architecture despite the additional fabrication steps.
Solution Approach 2:
The source connection structure is merged with the substrate architecture by forming vias directly through the substrate material. This integration eliminates the need for separate bonding or interconnection structures, reducing overall device complexity while achieving low source resistance.
Data Source
AI summary
The present invention features methods for forming a field effect transistor on a semiconductor substrate having gate, source and drain regions, with the gate region having a lateral gate channel. A plurality of spaced-apart trenches or through semiconductor vias (TSV) each having an electrically conductive plug formed therein in electrical communication with the gate, source and drain regions are configured to lower the resistance of the bottom source. A contact trench is formed adjacent to the source region and shorts the source region and a body region. A source contact is in electrical communication with the source region; and a drain contact in electrical communication with the drain region, with the source and drain contacts being disposed on opposite sides of the lateral gate channel.