Chip Scale Power LDMOS Device with Vertical Current Flow
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Solution Overview
Problem
Conventional semiconductor devices, particularly power MOS devices, face challenges in achieving a compact footprint and minimizing parasitic inductances, capacitances, and resistances due to packaging, which affects performance and heat dissipation, and are not well-suited for chip-scale designs due to vertical current flow requirements.
Innovation Solution
A semiconductor device with a macro-cell structure comprising LDMOS devices that utilize vertical current flow through a substrate to a common contact, featuring a bus structure with source and drain buses insulated from each other, allowing for direct formation of conductive bumps on the die, reducing the need for additional packaging and minimizing on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional packaging is used for power MOS devices, then the device is protected and connections are provided, but the footprint increases significantly (4 times larger than the die) and parasitic inductances, capacitances and resistances are added
Solution Approach 1:
The patent removes the traditional packaging structure entirely, extracting the protective and connective functions from a separate package and integrating them directly into the semiconductor die. The die itself becomes the package, with metallization layers and solder bumps providing both protection and connections, eliminating the need for an external package housing.
Solution Approach 2:
The patent merges the functions of the package (protection, connection provision) with the semiconductor die itself. The metallization layers and solder bumps are formed directly on the die, combining the device structure with the packaging structure into a single integrated unit, thereby eliminating the footprint overhead of separate packaging.
2Reliability
If conventional packaging is used for power MOS devices, then connections are provided, but parasitic inductances, capacitances and resistances are added that adversely affect device performance
Solution Approach 1:
The patent extracts the connection function from the external package and implements it directly on the die through metallization layers and solder bumps. This eliminates the long connection paths through package leads and bonding wires, removing the source of parasitic inductances, capacitances and resistances while maintaining reliable electrical connections.
3Reliability
If conventional packaging is used for power MOS devices, then connections are provided, but an additional thermal barrier is added between the die and its environment affecting heat dissipation
Solution Approach 1:
The patent removes the thermal barrier introduced by conventional packaging by eliminating the package housing and intermediate connection structures. The direct formation of solder bumps on the die creates a thermal pathway from the die through the solder bumps to the substrate, eliminating the thermal resistance of package leads, bonding wires, and package housing.
4Area of stationary object
If chip-scale approach is used with purely lateral current flow, then all connection terminals can be formed on the top side of the die, but a complex multilevel bus structure is required with narrow and thin bus stripes causing resistive voltage drop
Solution Approach 1:
The patent transitions from purely lateral current flow to a combination of vertical and lateral current flow by forming drain contacts that extend through the substrate to the bottom surface of the die. This dimensional change allows current to flow vertically through the substrate, eliminating the need for narrow lateral bus stripes and reducing resistive voltage drop while maintaining top-side terminal connections.
Data Source
AI summary
A semiconductor device includes at least one macro-cell device, the macro-cell device comprising a plurality of LDMOS devices. A first conductive layer is formed over the substrate, the first conductive layer providing source and drain contacts for the macro-cell device. A first isolation layer is formed over the first conductive layer and a second conductive layer is formed over the first isolation layer, the second conductive layer forming a drain bus and a source bus, wherein the buses are electrically coupled to the contacts through the first isolation layer. A second isolation layer is formed over the second conductive layer and insulates the source bus from the drain bus. A plurality of conductive bumps are formed over the second isolation layer, at least one of the conductive bumps directly contacting the drain bus and at least one of the conductive bumps directly contacting the source bus through the second isolation layer.