LDMOS Voltage Withstanding via Vertical Drift Extension
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Solution Overview
Problem
The existing LDMOS semiconductor devices face challenges in voltage withstanding performance due to high resistance in the drift region, leading to limited voltage handling capabilities.
Innovation Solution
A semiconductor structure and fabrication method that include a base substrate with P-type and N-type well regions, a first insulation layer dividing the N-type well region, and a gate structure with a first mask gate structure on the second well region, which increases the distance between the source and drain regions, enhancing the voltage withstanding performance by increasing the current path length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a drift region with low doping concentration is disposed between source and drain regions to improve voltage withstanding performance, then the voltage handling capability is improved, but the resistance of the drift region becomes relatively high
Solution Approach 1:
The patent segments the drift region into multiple zones with different doping concentrations. The first drift region has a first doping concentration while the second drift region has a second doping concentration, allowing different sections to serve different functions - one optimized for voltage blocking and the other for reduced resistive loss
Solution Approach 2:
Different regions of the drift zone are assigned different doping concentrations to optimize local properties. The first drift region uses one doping concentration to achieve high voltage blocking, while the second drift region uses a different doping concentration to reduce resistance and energy loss, creating local quality variations throughout the structure
2Ease of manufacture
If the channel length is determined by the difference between diffusion distances of arsenic and boron ions, then the LDMOS structure is formed with dual diffusion, but the voltage withstanding performance remains limited
Solution Approach 1:
The patent extends the drift region in the vertical dimension by creating a second drift region beneath the first, rather than relying solely on lateral diffusion distance differences. This vertical extension allows the current path to be lengthened and voltage withstanding performance to be improved while maintaining the ease of dual diffusion manufacturing process
3Reliability
If the distance between source and drain regions is increased to enhance voltage withstanding performance, then the voltage handling capability is improved, but the device area becomes larger
Solution Approach 1:
Instead of increasing the lateral distance between source and drain regions, the patent extends the drift region vertically by creating a second drift region beneath the first. This allows the effective distance to be increased in the vertical dimension rather than the lateral dimension, improving voltage withstanding performance without significantly increasing the device footprint area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively enhances the voltage withstanding performance of the semiconductor structure by increasing the distance between the source and drain regions, thereby improving the device's ability to handle high voltages.
Implementation Method 1
a first insulation layer over the base substrate in the second well region and dividing the second well region into a first region adjacent to the first well region, a second region away from the first well region and a third region under the first insulation layer
Implementation Method 2
Two ion implantation processes are performed in a same source/drain region. The doping ions in a first implantation process are arsenic ions with a higher concentration and the doping ions in a second ion implantation process are boron ions with a lower concentration
Implementation Method 3
a first stress layer on the first well region at a side of gate structure away from the first insulation layer; and a second stress layer on the second well regions at a side of the mask gate structure away from the isolation layer
Implementation Method 4
A high temperature activation process is performed after the ion implantation processes. Because the diffusion rate of the arsenic ions is greater than that of the boron ions, boron ions may laterally diffuse further below the interface between the gate structure and the substrate
Data Source
AI summary
Semiconductor structures and fabrication methods thereof are provided. An exemplary semiconductor structure includes a base substrate having a first well and a second well region; a first insulation layer over the base substrate and dividing the second well region into a first region adjacent to the first well region, a second region away from the first well region and a third region under the first insulation layer; a gate structure over the base substrate in the first well region and the first region of the second well region; a first mask gate structure on a portion of the second region adjacent to the first region; a first stress layer on the first well region at a side of gate structure away from the first insulation layer; and a second stress layer on the second well regions at a side of the mask gate structure away from the isolation layer.