LDMOS Drain Structure With Vertical Fin for Smaller High-Voltage Layouts
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Solution Overview
Problem
Current LDMOS devices have a large area due to the laterally diffused drain, leading to high cost and scaling challenges, which is unsuitable for high-frequency wireless communication applications.
Innovation Solution
A semiconductor device with a drain region comprising a well, doped regions, and drift regions, featuring a trench isolation structure and a gate stack, which is partially over the semiconductor layer and overlapping the drift regions, to optimize the device structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a laterally diffused drain structure is used in LDMOS devices, then high breakdown voltage and high output power are achieved, but the device area becomes large leading to high cost and scaling challenges
Solution Approach 1:
The patent transitions from a conventional planar drain structure to a three-dimensional FinFET structure. The drain region is formed as a vertical fin extending from the substrate surface into the substrate, creating a multi-dimensional architecture that increases effective drain area and improves breakdown voltage without increasing the lateral device footprint. This vertical dimensionality change resolves the contradiction between reliability and area.
Solution Approach 2:
The patent implements a nested structure where the gate electrode wraps around the fin structure in a U-shape configuration. The gate is positioned over and adjacent to the fin, with the fin nested within the gate structure. This nesting arrangement maximizes the gate-drain overlap area for high breakdown voltage while minimizing the lateral space required, thereby reducing overall device area.
2Reliability
If a laterally diffused drain structure is used in LDMOS devices, then high breakdown voltage and high output power are achieved, but scaling challenges arise
Solution Approach 1:
The patent employs vertical FinFET architecture that scales in the vertical dimension rather than requiring lateral scaling. The fin height and depth can be independently optimized to achieve higher breakdown voltages without increasing lateral dimensions, enabling continued scaling of device density while maintaining high voltage performance. This vertical scaling approach overcomes the limitations of conventional lateral scaling.
Solution Approach 2:
The patent applies different doping concentrations and material compositions to specific regions of the fin structure. The drain region of the fin has higher doping concentration near the substrate for high breakdown voltage, while the upper portions have lower doping for optimal carrier transport. This localized quality variation enables the structure to simultaneously achieve high breakdown voltage and good scaling characteristics.
Data Source
AI summary
A semiconductor device comprises a semiconductor layer over an insulator layer and a base layer under the insulator layer. A drain region comprises a well in the base layer, a doped region above and coupled with the well, a first drift region above and coupled with the first region, and a second drift region above the first doped region. The first doped region is at least partially in the insulator layer and the first drift region is at least partially in the semiconductor layer. A trench isolation structure is within the drain region and a gate stack is partially over the semiconductor layer and overlapping the first drift region.